DEPFET Transistor Gate Clearance via Drain-Side Contact Inversion
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Solution Overview
Problem
Conventional DEPFET transistors require high electric voltages for complete removal of signal electrons from the inner gate region, often resulting in incomplete clearance due to the potential barrier created by the source region.
Innovation Solution
The inner gate region extends partially to the clear contact, and the clear contact is relocated from the source side to the drain side, allowing signal electrons to be suctioned without overcoming the source region's potential barrier, with an optional drain/clear region that can be selectively activated to facilitate low-voltage clearance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the clear contact is located on the source side next to the DEPFET transistor, then the structure follows conventional design, but high electric voltages are required and complete removal of signal electrons is not achieved
Solution Approach 1:
The clear contact is relocated from the source side to the drain side of the DEPFET transistor, inverting the conventional position. This inversion allows signal electrons to be extracted from the inner gate region without needing to overcome the potential barrier created by the source region, thereby achieving complete clearance at lower voltages
Solution Approach 2:
The inner gate region is extended to reach the clear contact location at the drain side. This local structural modification creates a direct extraction path for signal electrons from the inner gate region to the clear contact, eliminating the need to overcome the source region's potential barrier
2Reliability
If the source region is highly p-doped to form a diode for depletion, then substrate depletion is achieved, but a potential barrier is created that hinders signal electron extraction
Solution Approach 1:
Instead of extracting signal electrons from the inner gate region through the source region (conventional approach), the clear contact is positioned at the drain side. This inversion bypasses the potential barrier created by the highly p-doped source region, allowing easy extraction of signal electrons while maintaining substrate depletion functionality
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables complete and efficient clearance of signal electrons with lower electric voltages, improving the sensitivity and operation of the semiconductor detector by ensuring signal electrons are concentrated below the channel for conductivity control.
Implementation Method 1
a separate clear contact is envisaged with the known DEPFET transistors that is located on the source side next to the DEPFET transistor itself and which suctions off the signal electrons gathered in the inner gate region with the application of a positive electric voltage
Implementation Method 2
the source region of the DEPFET structure produces in the semiconductor substrate a potential barrier which makes difficult the suctioning of the signal electrons gathered in the inner gate region
Implementation Method 3
a highly p-doped rear electrode being arranged on one surface of the semiconductor substrate, which rear electrode forms a diode poled in the blockage direction with the weakly n-doped semiconductor substrate and serves the purpose of depletion of the semiconductor substrate, wherein holes originating in the semiconductor substrate as a result of radiation effect are suctioned off by way of the rear electrode
Data Source
AI summary
The invention relates to a semiconductor structure, especially for use in a semiconductor detector. The semiconductor structure includes a weakly doped semiconductor substrate (HK) of a first or second doping type, a highly doped drain region (D) of a second doping type, located on a first surface of the semiconductor substrate (HK), a highly doped source region (S) of the second doping type, located on the first surface of the semiconductor substrate (HK), a duct (K) extending between the source region (S) and the drain region (D), a doped inner gate region (IG) of the first doping type, which is at least partially located below the duct (K), and a blow-out contact (CL) for removing charge carriers from the inner gate region (IG). According to the invention, the inner gate region (IG) extends in the semiconductor substrate (HK) at least partially up to the blow-out contact (CL) and the blow-out contact (CL) is located on the drain end relative to the source region (S).