Depletion-Mode ESD Protection Circuit for Leakage Reduction
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Solution Overview
Problem
Integrated circuits (ICs) are vulnerable to damage from electrostatic discharge (ESD) events, particularly due to high voltage differences between input/output terminals, which existing ESD protection devices may not adequately address without interfering with normal operation or increasing off-state leakage current.
Innovation Solution
The implementation of ESD protection circuits between the gate and drain terminals of depletion-mode transistors, utilizing a normally-on, depletion-mode pass transistor and level shifters like diodes to minimize leakage current and shunt ESD energy from the drain to the gate before dissipation to ground, without relying on enhancement-mode transistors or ground connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing ESD protection devices are used between input/output terminals, then ESD protection is provided, but they cannot adequately address high voltage differences without interfering with normal operation or increasing off-state leakage current
Solution Approach 1:
The patent introduces a depletion-mode transistor as an intermediary ESD protection device between the input/output terminal and ground. This intermediary component provides a controlled path for ESD current while maintaining high impedance during normal operation, thus protecting against ESD without significantly increasing off-state leakage current. The depletion-mode transistor acts as a voltage-controlled switch that remains off during normal operation and activates only during ESD events.
2Ease of operation
If ESD protection devices are configured to remain quiescent during normal operation, then normal IC operation is not interfered with, but the triggering voltage must exceed maximum normal operating voltage to avoid false activation
Solution Approach 1:
The patent utilizes the unique electrical parameters of depletion-mode transistors, specifically their negative threshold voltage characteristic, to create an ESD protection device that remains quiescent during normal operation but activates reliably during ESD events. By changing the transistor type from enhancement-mode to depletion-mode, the protection device responds to voltage changes in the opposite direction, allowing it to stay off during normal positive voltage operation and turn on during ESD overvoltage conditions.
3Reliability
If ESD protection devices provide a path to ground for discharge current, then vulnerable circuitry is protected, but the voltage limiter function must prevent voltage from reaching harmful levels without affecting normal operation
Solution Approach 1:
The depletion-mode transistor ESD protection device provides self-service voltage limiting through its inherent electrical characteristics. The device automatically limits voltage to safe levels by conducting ESD current to ground when the voltage exceeds the transistor's threshold, without requiring external control circuits or complex voltage sensing mechanisms. The transistor's own physical properties enable it to serve as both the protection switch and the voltage limiter simultaneously.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively protects ICs from ESD events with minimal impact on radio frequency performance and off-state leakage current, ensuring the ICs' reliability and operational integrity.
Implementation Method 1
a discharge path circuit and a trigger circuit coupled to, and configured to control, the discharge path circuit. The discharge path circuit and the trigger circuit are disposed between the gate terminal and the drain terminal
Implementation Method 2
utilizing a normally-on, depletion-mode pass transistor and level shifters like diodes to minimize leakage current
Implementation Method 3
shunt ESD energy from the drain to the gate before dissipation to ground
Data Source
AI summary
A device includes a transistor configured for depletion-mode operation, the transistor having a gate terminal and a drain terminal, and an electrostatic discharge (ESD) protection circuit coupling the gate terminal and the drain terminal. The ESD protection circuit includes a discharge path circuit and a trigger circuit coupled to, and configured to control, the discharge path circuit. The discharge path circuit and the trigger circuit are disposed between the gate terminal and the drain terminal.