Partially Depopulated Interconnection Arrays for PCB Signal Routing
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Solution Overview
Problem
Conventional printed circuit boards require multiple signal routing layers due to the obstructions caused by vias, which increases costs and reduces layout efficiency as ball grid array pitches decrease, making it difficult to route signals effectively.
Innovation Solution
A partially depopulated interconnection array layout is used, where certain locations are empty, reducing the number of vias and allowing for more flexible signal routing by separating power and signal connectors, thereby minimizing the number of signal routing layers needed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the pitch of ball grid arrays is reduced to conserve layout area, then area efficiency is improved, but the number of signal routing layers increases due to more vias obstructing signal paths
Solution Approach 1:
The patent extracts power connectors from the interconnection array, creating empty locations where power balls would normally be placed. This removal of power connectors eliminates the corresponding vias that would obstruct signal routing, thereby reducing the number of signal routing layers needed while maintaining the same ball grid array pitch
Solution Approach 2:
The patent separates power and signal connectors into different spatial arrangements, with power connectors positioned in specific locations that create systematic empty spaces. This dimensional reorganization allows signal traces to route more efficiently through the PCB layers without encountering power vias, reducing the vertical complexity of signal routing
2Adaptability or versatility
If multiple signal routing layers are used to accommodate signals, then signal routing capability is improved, but manufacturing cost increases
Solution Approach 1:
By removing power connectors from specific locations in the interconnection array, the patent eliminates the corresponding vias that would require additional signal routing layers. This reduction in via count directly decreases the number of PCB layers needed, simplifying manufacturing and reducing costs while maintaining adequate signal routing capability
3Adaptability or versatility
If vias are placed densely to support high-pin-count devices, then connectivity is improved, but trace routing becomes more difficult with more obstructions
Solution Approach 1:
The patent removes power connectors from the interconnection array, creating empty locations that eliminate corresponding vias. This selective extraction reduces via density in critical signal routing areas, making trace routing easier while maintaining necessary connectivity through the remaining optimized via placement
Solution Approach 2:
The patent segments the interconnection array into signal connector locations and power connector locations, with power connectors strategically positioned to create empty spaces. This segmentation allows signal traces to route through regions with fewer obstructions, improving ease of trace routing while preserving overall connectivity
Data Source
AI summary
In one embodiment, a ball grid array (BGA) of a packaged semiconductor device and a corresponding landing pad array of a printed circuit board each have a layout defined by an interconnection array having (i) an inner sub-array of locations having connectors arranged in rows and columns separated by a specified pitch and (ii) an outer rectangular ring of locations having connectors arranged in rows and columns separated by the specified pitch. The outer rectangular ring is separated from the inner sub-array by a depopulated rectangular ring having a width of at least twice the specified pitch, wherein the depopulated rectangular ring has no connectors. The outer rectangular ring has empty locations having no connectors. Some of those empty locations define depopulated sets that divide the outer rectangular ring into a number of different contiguous sets of locations having connectors that enable pin escape for connectors of the device's BGA.