Depth-Variable Trench Gate Layout for Low Channel and Contact Resistance
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Solution Overview
Problem
Trench gate semiconductor devices face challenges in reducing both channel resistance and contact resistance due to the small distance between trenches, which limits electron mobility and increases scattering at the gate interface.
Innovation Solution
The semiconductor device design includes trenches with a maximum distance between them less than 200 nm in depth, allowing for a FinFET effect that reduces channel resistance, and a larger trench distance at the surface to increase the contact area between the source region and the upper electrode, thereby reducing contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the distance between two adjacent trenches is reduced to form a channel in the entire body region, then channel resistance is reduced, but contact area between the source region and upper electrode is reduced
Solution Approach 1:
The patent applies local quality by creating different trench spacing configurations in different depth regions: small spacing (<200 nm) in the body region for low channel resistance, and larger spacing at the surface for adequate contact area. This spatial variation in geometric parameters resolves the contradiction between channel performance and contact performance.
Solution Approach 2:
The patent resolves the two-dimensional trade-off by introducing a depth dimension variable. The trench spacing is not uniform but varies with depth, allowing optimization of both channel region (deeper) and contact region (surface) simultaneously through three-dimensional geometric design.
2Speed
If the distance between two adjacent trenches is reduced, then electron mobility is improved through FinFET effect, but scattering at the gate interface increases
Solution Approach 1:
The patent applies local quality by restricting the small trench spacing configuration specifically to the body region where channel formation occurs, while maintaining larger spacing at the surface. This localized approach enables FinFET effect for improved electron mobility in the channel while avoiding excessive gate interface scattering in the contact region.
Data Source
AI summary
A trench gate semiconductor device includes a semiconductor substrate, first and second trenches, a gate insulating film, a gate electrode, and an upper electrode. The semiconductor substrate includes an n-type first semiconductor region in contact with the upper electrode, a p-type body region extending from the gate insulating film in the first trench to the gate insulating film in the second trench below the first semiconductor region, and an n-type second semiconductor region extending from the gate insulating film in the first trench to the gate insulating film in the second trench below the body region. A maximum value of a distance between the first trench and the second trench in a depth range in which the body region is disposed is less than 200 nm. The distance between the first trench and the second trench at the upper surface of the semiconductor substrate is larger than the maximum value.