Detecting High Impedance Floating FET Gates
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Solution Overview
Problem
Existing circuit simulation methods, such as SPICE variants, fail to reliably detect floating gates in electronic circuits, particularly MOSFET circuits, due to limitations in simulating real-world operating conditions and parasitic effects, leading to undetected design issues and potential circuit failures.
Innovation Solution
A computerized method and system that analyzes electronic circuit designs by scanning circuit stacks for floating FET gates using recursion and expression algorithms, identifying suspect nodes and victim FET gates, and determining if they produce high-impedance floating inputs, thereby detecting HI-Floating FET gates and other floating gate issues that prior art methods often overlook.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If prior art SPICE type circuit simulation methods are used, then circuit behavior can be verified against expectations, but floating gate issues remain undetected due to limitations in simulating real-world operating conditions and parasitic effects
Solution Approach 1:
The patent introduces an intermediary logical analysis layer that operates between the circuit netlist and the simulation results. This logical analyzer uses recursion algorithms to systematically examine circuit stacks and identify floating gate conditions that SPICE simulations miss, acting as a mediator that bridges the gap between theoretical simulation and real-world reliability detection
Solution Approach 2:
The patent segments the circuit analysis into discrete circuit stacks, where each stack represents a specific path or functional unit. By dividing the overall circuit into these manageable segments, the logical analyzer can systematically examine each stack for floating gate conditions without being overwhelmed by the complexity of the entire circuit, thereby improving detection precision
2Reliability
If SPICE simulations are run multiple times at many phases of design, then circuit behavior verification is performed, but the same reliability questions remain unanswered due to identical simulation approaches
Solution Approach 1:
The patent applies preliminary action by performing logical analysis of circuit stacks early in the design process, before simulation iterations. The recursion algorithm systematically identifies potential floating gate issues in advance, allowing designers to address reliability concerns before investing time in multiple simulation rounds, thereby reducing overall design iteration time
Solution Approach 2:
The patent creates a logical model copy of the circuit netlist that mirrors the actual circuit structure. This logical representation allows for rapid analysis of floating gate conditions without requiring physical circuit fabrication or extensive simulation, enabling reliability assessment to be performed quickly alongside design iterations
3Ease of operation
If prior art simulation methods operate on a question-answered basis with specific operating conditions, then targeted verification is achieved, but undetected design problems occur when accurate operating conditions are not provided
Solution Approach 1:
The patent implements self-service by enabling the logical analyzer to automatically examine all circuit stacks and identify floating gate issues without requiring manual specification of operating conditions. The recursion algorithm autonomously traverses the circuit netlist, detecting problems that would otherwise require expert knowledge and extensive setup, thereby maintaining ease of operation while improving detection capability
Data Source
AI summary
Method for automatically analyzing complex electronic circuit designs for generalized types of floating FET gate circuit design errors that encompass both standard floating gate issues and previously difficult-to-find high impedance situations. The invention views electronic circuits as comprising a large number of “circuit stacks”, each stack having a small number of electronic devices between a given power and ground rail within the circuit. The invention uses a computer processor and a recursion algorithm to automatically analyze circuit netlists, determine the different circuit stacks, stack input-output functions, and stack devices, and use an expression algorithm to determine a logical expression of the given stack's input-output function. The invention determines nodes that are connected to various FET gates, and checks if various given FET gates are connected to any DC-pin devices that might produce floating or high-impedance floating input to these FET gates, thus causing that particular FET gate to float.