Device Isolation Layer Formation Using Dual Insulation and Liner Protection
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Solution Overview
Problem
Conventional methods for forming device isolation layers in semiconductor and non-volatile memory devices face challenges such as uneven etch rates and damage to critical layers like tunnel dielectric and charge storage layers, particularly due to the high aspect ratio trenches and plasma processes used in forming HDP oxide layers.
Innovation Solution
A method involving a first insulation layer with a higher etch rate and a second insulation layer with a lower etch rate is employed, where the second layer is formed over a liner oxide layer to prevent damage and ensure uniform etch rates, using materials like HDP oxide for the second layer to avoid voids and control effective field oxide height.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If HDP oxide is used to form the insulation layer, then the device isolation layer can be formed, but the plasma process damages the tunnel dielectric layer and charge storage layer
Solution Approach 1:
A liner oxide layer is introduced as an intermediary protective layer between the HDP oxide insulation layer and the critical tunnel dielectric/charge storage layers. The liner oxide layer absorbs the plasma damage during HDP oxide formation, preventing direct damage to the sensitive memory layers while allowing the device isolation layer to be properly formed
Solution Approach 2:
The liner oxide layer is formed beforehand on the substrate before depositing the HDP oxide insulation layer. This pre-formed protective layer cushions and protects the underlying critical layers from the harmful plasma effects during subsequent HDP oxide deposition and processing steps
2Reliability
If the aspect ratio of device isolation trench increases, then device integrity is improved, but filling the trench becomes more difficult
Solution Approach 1:
The flowable oxide material is deposited in a liquid or semi-liquid state that can flow into and completely fill high aspect ratio trenches without voids. The material's flowing property allows it to conform to the trench geometry and eliminate empty spaces that would be difficult to achieve with conventional solid or gaseous materials
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach prevents the formation of voids and moats, ensures uniform etch rates across multiple layers, and protects critical layers, thereby improving data retention characteristics and maintaining the integrity of semiconductor and non-volatile memory devices.
Implementation Method 1
After filling the device isolation trench with the flowable oxide, a dense insulation layer for forming a device isolation layer may be formed through a thermal treatment. The thermal treatment eliminates gas components from the flowable oxide.
Implementation Method 2
During the process, the chemical structure of the PSZ layer is changed into a SiO2 layer.
Implementation Method 3
an insulation layer is formed of a high density plasma (HDP) oxide to form a device isolation layer
Implementation Method 4
a device isolation trench is formed by etching a substrate to a predetermined depth
Data Source
AI summary
A method for forming a device isolation layer of a semiconductor device or a non-volatile memory device is provided. A method for forming a device isolation layer of a semiconductor device includes: forming trenches having a first predetermined depth by etching a substrate; forming a first insulation layer having a second predetermined depth inside the trenches; forming a liner oxide layer having a predetermined thickness on internal walls of the trenches with the first insulation layer formed therein; and forming a second insulation layer for forming a device isolation layer over the substrate with the liner oxide layer formed therein, wherein the second insulation layer has a lower etch rate than that of the first insulation layer.