DEVS Chip Clock Frequency Distribution for Power Optimization
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Solution Overview
Problem
Current systems that integrate sensing, communication, and computation do not efficiently exploit the predictive capabilities of internal models to optimize computational requirements, leading to excessive power consumption and over-engineering, especially in energy-constrained environments where physical stimuli and application modes are variable.
Innovation Solution
The implementation of a DEVS (Discrete Event Systems) hierarchical, modular model construction methodology that characterizes the system's current state and adjusts execution behaviors to match intrinsic computational demands, reducing unnecessary computations and power consumption by distributing clock frequencies based on component rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If systems run as fast as needed by the most demanding component, then real-time computational requirements are met, but power consumption increases excessively
Solution Approach 1:
The patent implements dynamic clock frequency distribution across system components based on their instantaneous computational demands. Each component receives a customized clock frequency that adapts in real-time to its current workload, rather than running all components at a uniform high frequency. This dynamic adjustment allows the system to meet real-time requirements of demanding components while reducing power consumption of less demanding components.
Solution Approach 2:
The system applies different clock frequencies to different components based on their specific computational requirements. Instead of a uniform high-frequency clock distributed to all components, each component receives a locally optimized frequency that matches its intrinsic rate and current demands, creating a non-uniform frequency distribution that optimizes overall system power efficiency while maintaining real-time performance where needed.
2Use of energy by moving object
If voltage and frequency scaling techniques are used, then power consumption is reduced, but the system does not exploit predictive capabilities of internal models
Solution Approach 1:
The system uses internal models to predict future computational requirements of components before they actually need computation. By anticipating which components will need processing power and when, the system can pre-adjust clock frequencies and voltage levels accordingly, enabling proactive power management that exploits predictive capabilities rather than merely reacting to current workload states.
Solution Approach 2:
The system implements a feedback mechanism where internal models continuously monitor system state, environmental conditions, and component performance to predict future computational demands. This feedback loop enables the power management system to adjust clock frequencies and voltage scaling in response to predicted rather than just current needs, creating an adaptive system that learns and optimizes based on observed patterns.
3Reliability
If worst-case execution requirements are assumed, then timing constraints are guaranteed, but systems become over-engineered with excessive power consumption
Solution Approach 1:
Instead of applying worst-case clock frequencies to all components (excessive action), the system applies clock frequencies that are partially sufficient - exactly matching each component's actual computational needs. The DEVS model predicts and determines the precise frequency required for each component, avoiding the waste of running components at unnecessarily high frequencies while still guaranteeing timing constraints are met when needed.
Solution Approach 2:
The system dynamically changes clock frequency parameters based on predicted computational requirements rather than maintaining fixed worst-case parameters. By using DEVS internal models to determine appropriate frequency levels, the system adjusts operational parameters in real-time, transitioning from static over-engineered configurations to dynamic, demand-matched configurations that reduce complexity and power consumption while maintaining reliability.
4Speed
If uniform high clock frequency is distributed to all components, then real-time performance is ensured, but energy efficiency is compromised
Solution Approach 1:
The patent implements a non-uniform clock frequency distribution where each component receives a locally optimized frequency based on its specific computational characteristics and current demands. High-frequency clocks are applied only to components that require real-time performance, while other components operate at lower frequencies, creating a spatially differentiated frequency landscape that optimizes both speed and energy efficiency.
Solution Approach 2:
The system transitions from a static uniform frequency distribution to a dynamic, component-specific frequency distribution. Clock frequencies are continuously adjusted based on real-time predictions from DEVS models, allowing the system to optimize the speed-energy tradeoff dynamically rather than committing to a fixed high-frequency configuration that wastes energy during low-demand periods.
Data Source
AI summary
Embodiments disclose a DEVS chip is used to send only meaningful data in the system and therefore saves energy and increase processing speed. The sensor nodes communicate with an office chip temperature sensor or power management. The data acquired by the senor nodes is used for evaluating of the quantizer which has a stored quantum size and a stored temperature value or power level. If the difference between a stored temperature or a stored power level and a new temperature or a new stored power level is greater or equal to the predetermined quantum size, the new temperature or new power level is saved. The quantizer generates an event that transmits the temperature or the power level with quantum value to the sensor nodes. The small changes in the difference does not effect the system beyond the quantizer.