A DEVS chip distributes clock frequencies based on component rates to reduce unnecessary computations.
Dynamic voltage and frequency scaling adjusts processor communication fabric parameters to reduce power consumption while maintaining system performance.
A power-complementing circuit generates second power consumption to mask logic operations in a processor.
Acceleration sensors detect vibrations to wake systems from deep sleep, extending battery life by reducing current draw from hundreds of milliamps to microamps.
Segmentation and universality principles reduce weight and volume by allowing users to attach only needed functional modules via a universal coupler.
Segmenting backup power supplies into modules protects specific components during failures, reducing space usage and energy waste.
A removable capacitor power pack supplies backup energy to solid state storage processors and memory modules.
An auxiliary processor handles basic functions while the main CPU stays off, reducing battery drain and enabling instant-on connectivity.
A computing device stores a content screen for display on an electronic paper type display.
A USB control circuit with switch circuits enables flexible role swapping between upstream and downstream ports.
Selective PSE and PD port configuration provides power redundancy during supply failures.
A dedicated standby power pin isolates control logic from main supply rails, reducing transistor leakage current during low-power operation.
A power throttling queue uses a throttling circuit to dynamically adjust its operational size based on workload conditions.
A content delivery system adjusts item selection using battery status data.
A centralized backup power source supplies direct DC voltage to multiple server motherboards.
An active edge conducts heat from the processor to an exposed metal surface for passive dissipation.
A server method applies selected energy conservation options to virtual universe portions associated with an avatar.
Hierarchical power management coordinates supervisor and supervisee units across diverse dice, resolving complexity in multi-die thermal control.
A power management system adjusts real machine states based on virtual machine loads.
A single detection circuit switches modes to monitor load open and ground faults, reducing component count.
A power management unit sets internal clock signal timing points based on module identification data to generate stable supply voltages.
A rack management controller generates power consumption profiles for processing nodes to dynamically regulate power budgets.
Completion detection logic bridges delay-insensitive NCL processors and synchronous memory, resolving unpredictable gate delays to minimize power consumption.
Zone-level backup PDUs with automatic transfer switches reduce capital costs by providing oversubscribed redundancy without full system duplication.
System software components notify via API to perform pre-hibernation activities before snapshot creation.
Aggregating device idle durations allows platforms to select deeper sleep states while maintaining quality of service.
Monitoring power consumption allows proactive fan speed adjustment, eliminating the time lag inherent in temperature-threshold cooling systems.
A controller manages parallel processor activity by incrementally adjusting core clock frequency and activating computing element portions.
A power management micro-controller sets node peak power thresholds to dynamically adjust CPU operating frequencies based on real-time workload data.
A power discharge control device generates a signal to execute a controlled power discharge process.
A storage controller measures host exit latency to select low power state entrance actions.
A power supply control unit switches between battery and radio wave sources to preserve volatile memory settings during low-power modes.
A USB device switches operating modes to enable direct driver installation without manual resets.
A dual protection device combines a mechanical fuse and an electronic fuse in series to safeguard downstream circuitry from electrical faults.
A proxy interface emulates COM server DLL exports to enable safe removal of malicious code without crashing client applications.
A timing estimation device calculates bus delays to adjust access requests within a function verification model.
A trigger circuit monitors subsystem power consumption and activates telemetry mode when levels exceed a threshold, enabling precise thermal management.
A smart device remains awake to monitor user-defined events without additional wake-up commands.
An interrupt monitor captures interrupts while the controller powers down, retaining signals for later processing.
A resource hotplug managing system evaluates scenario data based on context information to control resource activation.
A clock management unit uses dedicated hardware control circuits to manage clock signals for intellectual property blocks in semiconductor devices.
A system core dynamically adjusts clock frequencies across multiple processing cores to match real-time workload demands.
Dynamic voltage adjustment prevents processor aging by scaling down power consumption during low workloads.