Memory Module Power Management Unit Clock Timing Control
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Solution Overview
Problem
There is a need for a technology that can stably generate internal power supply voltages using an external power supply voltage in memory modules equipped with a power management unit (PMU).
Innovation Solution
A memory module with a power management unit (PMU) that communicates with a serial presence detector to set the on-time and off-time points of an internal clock signal based on a module ID, and generates internal power supply voltages in response to this clock signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple memory modules are mounted on a main board, then memory capacity is increased, but power supply voltage instability occurs due to simultaneous power consumption
Solution Approach 1:
The power management unit generates an internal clock signal with periodic on-time and off-time points to control the switching of power supply voltage generation. This periodic action allows different memory modules to operate in staggered time intervals, preventing simultaneous power consumption that causes voltage instability.
Solution Approach 2:
The system dynamically adjusts the on-time point and off-time point of the internal clock signal based on the module ID. This dynamic timing adjustment ensures that memory modules at different positions consume power at different times, resolving the contradiction between having multiple modules and maintaining stable power supply voltage.
2Adaptability or versatility
If power management unit is integrated in each memory module, then power management flexibility is improved, but power supply voltage instability occurs across modules
Solution Approach 1:
Each power management unit is configured with position-specific timing parameters (on-time point and off-time point) determined by its module ID. This local quality differentiation ensures that while each module independently manages its own power, the collective system maintains voltage stability through staggered operation timing.
3Device complexity
If internal clock signal timing is standardized across all memory modules, then system simplicity is maintained, but power supply voltage instability occurs in multi-module configurations
Solution Approach 1:
The power management unit uses a universal internal clock signal generation mechanism that can be configured with different timing parameters. The same hardware structure serves multiple functions by adjusting the on-time point and off-time point based on module ID, maintaining system simplicity while enabling position-specific power management.
Data Source
AI summary
A memory module includes a serial presence detector (SPD) configured to detect a module identification (ID) through at least one module position identification terminal, and generate at least one of the module ID and a register address corresponding to the module ID. A power management unit (PMU) is responsive to at least one of the module ID and the register address generated by the SPD. The PMU is configured to set an on-time point and/or an off-time point of an internal clock signal based on at least one of the module ID and the register address corresponding to the module ID, and further configured to generate at least one internal power supply voltage in response to the internal clock signal. A plurality of memory devices are also provided, which are configured to receive the at least one internal power supply voltage and perform an operation in response to command/address signals.