Power-Complementing Circuitry for Masking Processor Power Consumption
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Solution Overview
Problem
Modern microprocessors face challenges in masking power consumption associated with logic operations, particularly during cryptographic processes, as existing techniques fail to accurately obscure power consumption, making them vulnerable to reverse engineering and attacks like Differential Power Analysis (DPA).
Innovation Solution
The implementation of a power-complementing circuitry that generates a second power consumption complementary to the first, combining to produce a substantially constant power consumption on a clock-cycle-by-clock-cycle basis, using header circuitry and transistors with varying threshold voltages and sizes to control and mask the power consumption of logic circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional cryptographic devices use power consumption concealment techniques, then security against DPA attacks is improved, but the power consumption masking is inaccurate and vulnerable to reverse engineering
Solution Approach 1:
The patent introduces an intermediary power-complementing circuit that generates complementary power consumption to mask the actual power consumption of cryptographic operations. This mediator circuit receives control signals and generates opposing power consumption patterns that cancel out the original consumption signature, making it impossible for attackers to extract cryptographic keys through DPA analysis.
Solution Approach 2:
The patent dynamically changes power consumption parameters by controlling the power-complementing circuit to generate variable complementary power consumption based on control signals. This allows the system to adaptively mask different cryptographic operations with varying power consumption patterns, preventing attackers from identifying specific operations or extracting keys through statistical analysis.
2Reliability
If power-complementing circuitry is added to mask power consumption, then security is improved, but device complexity increases
Solution Approach 1:
The patent segments the power consumption masking function into distinct modular components: power-complementing circuitry that generates complementary power consumption, control circuitry that generates control signals, and header circuitry that interfaces with the cryptographic processor. This segmentation allows each component to be optimized independently and simplifies integration into existing cryptographic devices.
Solution Approach 2:
The power-complementing circuit is designed with multi-functionality to handle various cryptographic operations (encryption, decryption, key generation) through a single unified architecture. The circuit responds to different control signals to generate appropriate complementary power consumption patterns for different operations, eliminating the need for separate masking circuits for each cryptographic function.
3Reliability
If power consumption is masked to prevent DPA attacks, then information security is improved, but the ability to monitor and debug processor operations is reduced
Solution Approach 1:
The patent extracts the power consumption monitoring function from the masked power consumption signal by using separate control and measurement pathways. The control circuitry generates control signals for the power-complementing circuit based on the desired cryptographic operations, while monitoring circuitry can independently measure actual power consumption for debugging purposes without compromising the security masking during normal operation.
Solution Approach 2:
The system dynamically switches between security mode and debugging mode. During normal cryptographic operations, the power-complementing circuit is activated to mask power consumption. During debugging or monitoring operations, the masking can be temporarily disabled or adjusted to allow legitimate observation of power consumption patterns while maintaining security during actual cryptographic processing.
Data Source
AI summary
An apparatus for masking power consumption associated with one or more operations of a logic circuitry of a processor. The apparatus comprises power-complementing circuitry configured to provide a second power consumption to directly power-complementing the power consumption associated with the one or more operations of the logic circuitry. The second power consumption complements the power consumption associated with the one or more operations of the logic circuitry. The apparatus further comprises header circuitry configured to enable a common node to vary in voltage corresponding to the one or more operations of the logic circuitry. The power-complementing circuitry and the header circuitry are each coupled to the logic circuitry at the common node.