Parallel Processor Current Control via Incremental Activation
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Solution Overview
Problem
Parallel processors experience large instantaneous current changes during transitions between idle and active states, leading to voltage spikes or droops that can cause performance loss or functional failure, and existing methods to address this issue increase manufacturing costs.
Innovation Solution
A system and method that monitor the activity of computing elements in parallel processors to predict transitions and control the core clock frequency or selectively activate portions of the array to minimize these current changes, using incremental adjustments to the clock frequency or activation of computing elements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the array of computing elements is activated from idle state, then processing capability is improved, but large instantaneous current changes occur causing voltage spikes or droops
Solution Approach 1:
The system performs preliminary actions by incrementally activating portions of the computing element array before full activation is needed. The controller divides the array into multiple portions and activates them sequentially over multiple cycles, preparing the system for full processing capability while avoiding instantaneous current spikes that would compromise voltage stability
Solution Approach 2:
The computing element array is segmented into multiple portions that can be independently controlled. The controller activates these portions sequentially rather than all at once, which divides the total current draw into smaller incremental steps, thus maintaining voltage stability while still achieving the required processing capability
2Productivity
If the array is activated to meet processing demands, then productivity is improved, but manufacturing cost increases due to over-engineering the processor package and power grid
Solution Approach 1:
The system implements dynamic activation where the controller adjusts which portions of the computing element array are active based on actual processing demands. This dynamic approach allows the processor to scale its active computing resources up or down, avoiding the need for a permanently over-engineered power grid and package design that would be required if all elements needed to be simultaneously supportable at full power
3Productivity
If the core clock frequency is increased to improve processing speed, then productivity is improved, but instantaneous current changes increase causing performance loss
Solution Approach 1:
The controller performs preliminary frequency adjustment by incrementally increasing the core clock frequency across multiple activation cycles rather than jumping to the maximum frequency immediately. This gradual ramp-up allows the power delivery network to adapt to increasing current demands, preventing voltage droops that would cause performance loss while still achieving high processing speeds
Data Source
AI summary
Systems and methods are disclosed method for controlling instantaneous current changes in parallel processors with arrays of parallel computing elements, such as neural processors. An exemplary method comprises monitoring the array of computing elements and determining a transition from a first activity level of the array to a second activity level of the array, such as an idle-to-active or active-to-idle transition. Once a transition is determined, the array is selectively controlled to minimize the instantaneous current change from the transition from the first activity level to the second activity level.