SSD Controller Host Exit Latency Optimization

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Solution Overview

Problem

There is a need to improve the low power state entrance of data storage devices, such as solid state drives (SSDs), to reduce device-exit-latency and maintain quality of service (QoS) while minimizing power consumption.

Innovation Solution

A controller in the data storage device determines the host exit latency and selects a group of low power state entrance actions from a plurality of groups based on the completion wake up time and the host exit latency, ensuring that the completion wake up time is closest to and less than or equal to the host exit latency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by stationary object

If the data storage device transitions to firmware active idle state to reduce power consumption, then power usage is decreased, but device exit latency increases when waking up from low power state

Engineering Contradiction:
Improvepower consumptionVSAvoiddevice exit latency
Core Design Contradiction:
Use of energy by stationary objectVSLoss of time

Solution Approach 1:

The system performs preliminary actions by measuring host exit latency in advance and pre-configuring the appropriate firmware active idle state entrance actions before actually entering the low power state. This allows the device to be optimally prepared for wake-up, ensuring that when a command arrives, the device can exit latency optimally without unnecessary delays.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system dynamically adjusts the firmware active idle state entrance actions based on measured host exit latency values. Different groups of actions are selected from a plurality of available actions, with each group having different completion wake-up times. This dynamic adaptation allows optimization of the trade-off between power savings and exit latency for each specific host.

Inventive Principle:
Principle #15Dynamics

2Use of energy by stationary object

If more firmware active idle state entrance actions are performed to reduce power consumption, then power savings increase, but completion wake up time increases

Engineering Contradiction:
Improvepower savingsVSAvoidcompletion wake up time
Core Design Contradiction:
Use of energy by stationary objectVSDuration of action of moving object

Solution Approach 1:

The system changes the parameter of completion wake-up time by selecting different groups of firmware active idle state entrance actions with different durations. Each group is designed to have a completion wake-up time that matches or is less than the measured host exit latency, thereby optimizing power savings while ensuring timely wake-up.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The system applies partial action by selecting only the necessary portion of firmware active idle state entrance actions required to achieve adequate power savings without excessive wake-up time. The selection is based on matching the host exit latency, ensuring that not all possible actions are performed, but only those needed for optimal performance.

Inventive Principle:
Principle #16Partial or excessive action

3Loss of time

If the host device sends wake up indication quickly to reduce latency, then device response time improves, but power consumption optimization is compromised

Engineering Contradiction:
Improveresponse timeVSAvoidpower consumption optimization
Core Design Contradiction:
Loss of timeVSUse of energy by stationary object

Solution Approach 1:

The system uses feedback from measuring actual host exit latency to adjust the firmware active idle state entrance actions. By continuously monitoring and adapting to the host's wake-up characteristics, the system optimizes power consumption while maintaining fast response times, creating a closed-loop optimization system.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS12332720B2Low power optimization based upon host exit latency
Publication Date: 2025.06.17 SANDISK TECHNOLOGIES LLC
  • US12332720B2 patent drawing
  • US12332720B2 patent drawing
  • US12332720B2 patent drawing

AI summary

There is a tradeoff between the amount of power consumption decreased and the latency needed to return a data storage device back to an operational power mode. When the data storage device receives a wake up indication from a host device, a controller of the data storage device initiates a counter in order to determine a host exit latency. Based on the host exit latency, the controller determines a group of low power state entrance actions from a plurality of groups to perform during a next entrance into a firmware active idle state based on an associated completion wake up time and the host exit latency. The controller selects the group whose completion wake up time is closest to the host exit latency and less than or equal to the host exit latency. The controller performs the selected groups low power state entrance actions during a next entrance into the firmware active idle state.