NCL Processor Interface for Synchronous Memory Timing
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Solution Overview
Problem
Asynchronous processors operating near or below the threshold voltage face significant challenges in predicting delay times due to varying delays across logic gates, making it difficult to interface effectively with synchronous memory systems.
Innovation Solution
The implementation of null convention logic (NCL) processors, which use dual-rail or multi-rail logic and threshold gates, along with specific interface mechanisms to synchronize with synchronous memory, including the use of acknowledge signals to manage cycles and generate clocks, ensuring proper data transfer and cycle initiation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If asynchronous processors operate near or below threshold voltage to minimize power consumption, then power consumption is reduced, but delay time prediction becomes unreliable due to variations across logic gates
Solution Approach 1:
The patent introduces an interface circuit as an intermediary between the asynchronous processor and synchronous memory. This interface includes completion detection logic that monitors when all logic gates have finished their operations and generated valid output values, bridging the gap between the delay-insensitive asynchronous domain and the timing-critical synchronous domain.
Solution Approach 2:
The patent implements feedback mechanisms through completion detection logic that tracks the operational status of logic gates. The system uses feedback signals to determine when all gates have completed their computations and produced valid outputs, enabling reliable interface timing without requiring precise delay predictions for each gate.
2Use of energy by moving object
If asynchronous processors use delay-insensitive logic to operate at lower voltages, then power consumption decreases, but interfacing with synchronous memory becomes difficult due to unpredictable gate delays
Solution Approach 1:
The interface circuit serves as a mediator that translates between the delay-insensitive asynchronous protocol and the timing-sensitive synchronous memory interface. It includes completion detection logic that converts unpredictable gate delays into reliable completion signals that the synchronous memory can use for timing.
Solution Approach 2:
The patent changes the timing parameters of the asynchronous processor outputs by introducing completion detection logic that waits until all logic gates have finished their operations. This transforms the variable delay characteristic into a deterministic completion signal that can be used for synchronous interface timing.
3Ease of operation
If synchronous processors use a common clock signal for operation, then timing synchronization is simplified, but power consumption increases due to higher operating voltage requirements
Solution Approach 1:
The patent segments the processing system into two distinct domains: an asynchronous processor core that operates at low voltage for minimal power consumption, and a synchronous interface circuit that handles timing-critical operations. This segmentation allows each part to operate in its optimal voltage and timing regime.
Solution Approach 2:
The patent introduces dynamic voltage scaling by operating the processor core at near-threshold or below-threshold voltages while using a synchronous clocked interface at higher voltages only where needed for memory interfacing. This dynamic approach optimizes power consumption while maintaining necessary timing synchronization.
Data Source
AI summary
Self-timed processing systems and methods of operating self-timed processing systems are disclosed. A self-timed processing system includes an asynchronous null convention logic (NCL) processor, a memory that accepts input signals on an active edge of a memory clock signal, and logic to combine a first acknowledge signal and a second acknowledge signal to generate the memory clock signal. The first acknowledge signal indicates input signals are ready to be accepted by the memory. The second acknowledge signal indicates data signals previously output from the memory have been accepted by the processor.