Distributed DFE Summation Latch for High-Speed Receiver Detection
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Solution Overview
Problem
High-speed data receivers face challenges in timely computation and distribution of Decision Feedback Equalization (DFE) corrections due to the need to combine multiple correction terms and the use of multiple parallel processing phases, which can lead to reduced detector amplification and gain.
Innovation Solution
The method involves pre-charging sets of nodes to generate differential output signals, combining data signal nodes with DFE correction nodes to produce a summation of DFE correction factors, and applying these corrections to achieve efficient computation and distribution within the data receiver system without significant impact on detector gain.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple parallel processing phases are used to extend detection time, then detection accuracy is improved, but computation and distribution of DFE corrections becomes more difficult and time-consuming
Solution Approach 1:
The patent divides the DFE correction computation into multiple parallel processing phases, where each phase handles a subset of correction terms. This segmentation allows the system to maintain high detection accuracy through multiple processing stages while managing complexity by distributing computations across independent parallel units rather than requiring sequential processing of all corrections.
2Measurement precision
If multiple parallel processing phases are used to extend detection time, then detection accuracy is improved, but detector amplification and gain are reduced
Solution Approach 1:
The patent applies DFE corrections in advance during the parallel processing phases before the final detection stage. By pre-computing and applying correction terms across multiple phases, the system achieves high detection accuracy without requiring excessive amplification or gain in the final detection stage, thus avoiding the trade-off between extended processing and reduced amplification.
3Productivity
If DFE corrections are computed and distributed timely, then high data rates are supported, but circuit delays and processing elements increase
Solution Approach 1:
The patent segments DFE correction computations across multiple parallel processing phases, allowing each phase to compute and distribute a subset of corrections independently. This segmentation enables timely computation and distribution of corrections at high data rates while minimizing overall circuit delays by avoiding sequential processing of all correction terms.
Data Source
AI summary
Pre-charging two or more sets of nodes to set a differential output of a multi-input summation latch connected to the two or more sets of nodes in a pre-charged state, the two or more sets of nodes comprising a set of data signal nodes and a set of DFE correction nodes, in response to a sampling clock, generating a differential data voltage and an aggregate differential DFE correction signal, and generating a data decision by driving the differential output of the multi-input summation latch into one of two possible output states according to a summation of the differential data voltage signal and the aggregate differential DFE correction signal and subsequently holding the data decision by holding the differential output of the multi-input summation latch in a latched state for a duration determined by the sampling clock.