Automated DFT Channel Insertion in Chip Modules
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Solution Overview
Problem
The complexity of Integrated Circuit (IC) design and varying Design for Testability (DFT) requirements across different modules and hierarchies lead to errors and inefficiencies in the IC development cycle, as designers struggle to manage and update DFT design entities across multiple code hierarchies and modules.
Innovation Solution
An information processing method and device that determines the need for DFT processing in a chip, establishes a DFT signal transmission channel layer by layer, and generates a channel file using corresponding port signals, allowing for automated insertion and verification of DFT channels across the chip, reducing manual intervention and enhancing reusability across different code environments and design requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If manual updates and modifications of DFT design entities are performed across multiple code hierarchies and modules, then design flexibility and adaptability are maintained, but human resources are wasted and the IC development cycle is prolonged
Solution Approach 1:
The system performs self-service through automated detection and update of DFT design entities. The processing unit automatically identifies modules requiring DFT processing, establishes signal transmission channels, and updates design entities across hierarchies without requiring manual intervention, thereby reducing human resource waste and accelerating the development cycle
Solution Approach 2:
The system changes the state of DFT design entities by automatically updating their parameters and configurations across multiple code hierarchies. By detecting modules needing DFT processing and establishing signal transmission channels, the system dynamically modifies design entity parameters to meet varying DFT requirements without manual reconfiguration
2Adaptability or versatility
If different DFT design requirements are introduced to different modules and code hierarchies, then design adaptability is improved, but errors increase due to differences in individual understanding and signal naming
Solution Approach 1:
The system introduces an intermediary processing unit that standardizes the interface between different DFT design requirements and modules. This intermediary automatically detects modules needing DFT processing, establishes unified signal transmission channels, and manages the instantiation relationships across hierarchies, eliminating errors caused by individual understanding differences and inconsistent signal naming
Solution Approach 2:
The system implements a universal DFT processing mechanism that can handle different DFT design requirements across multiple modules and code hierarchies through a single standardized approach. The processing unit universally detects modules, establishes signal transmission channels, and manages instantiation relationships, providing a multi-functional solution that adapts to various DFT requirements while maintaining consistency and reducing errors
3Reliability
If DFT design entities pass through multiple hierarchies and modules of codes, then comprehensive testability is achieved, but manual communication and exchanges between designers and integrators are required, increasing time consumption
Solution Approach 1:
The system achieves self-service by automatically detecting modules requiring DFT processing across multiple hierarchies, establishing signal transmission channels, and updating design entities without requiring manual communication between designers and integrators. The automated processing maintains comprehensive testability while eliminating time-consuming manual coordination
Solution Approach 2:
The system implements feedback mechanisms where the processing unit continuously detects modules needing DFT processing, establishes signal transmission channels, and updates design entities across hierarchies based on detected requirements. This automated feedback loop ensures comprehensive testability is maintained across all modules while eliminating manual communication time
Data Source
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AI summary
An information processing method is disclosed, including: determining a module for which a design for testability, DFT, processing is needed, in a chip; establishing, in an including manner, a DFT signal transmission channel in the module for which the DFT processing is needed, and generating a channel file by using a corresponding port signal; and interpenetrating the DFT signal transmission channel layer by layer until the top layer of the chip, according to an instantiated reference relationship. An information processing device and a computer storage medium are also disclosed.