Diamond-Substrated Chiplet Packaging for Direct Jet Cooling
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Solution Overview
Problem
Thermal management challenges in high-power advanced chip packages are exacerbated by the integration of diamond substrates, which are thinner and harder than standard semiconductor materials, causing issues with standard chip-on-wafer-on-substrate (CoWoS) processing, including surface smoothness, thickness tolerance, gap filling, and thermal resistance, as well as CTE mismatch with copper layers.
Innovation Solution
A modified CoWoS process flow that includes a diamond-containing dielet bonded to a thinned semiconductor logic die, allowing direct jet impingement cooling, with minimal adaptation to existing processes, using techniques like laser-assisted bonding and temporary filler materials to maintain mechanical integrity and avoid CTE mismatch.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If diamond substrates are integrated into CoWoS processing, then heat dissipation efficiency is improved, but manufacturing complexity increases due to surface smoothness and thickness tolerance issues
Solution Approach 1:
The diamond substrate is segmented into multiple thickness zones with different polishing degrees. The center region maintains higher thickness for heat dissipation, while edge regions are thinned to match standard semiconductor thickness tolerances, allowing integration into existing CoWoS processes without requiring uniform ultra-precise polishing across the entire substrate.
Solution Approach 2:
Different regions of the diamond substrate are assigned different surface qualities and thickness characteristics. The central active area retains high thermal conductivity and appropriate thickness for heat spreading, while peripheral areas are modified to accommodate standard packaging processes, thereby resolving the conflict between heat dissipation performance and manufacturing complexity.
2Loss of energy
If diamond substrates are used, then thermal resistance is reduced, but mechanical integrity deteriorates due to hardness and thickness differences
Solution Approach 1:
The diamond substrate parameters are optimized by controlling thickness distribution and surface finish. The substrate thickness is maintained within 50-200 micrometers in the center for optimal thermal performance, while edge thickness is reduced to match surrounding semiconductor components. Surface roughness is controlled within specific ranges to balance thermal conductivity with mechanical robustness during handling and bonding processes.
3Adaptability or versatility
If standard CoWoS processing is used with diamond substrates, then process compatibility is improved, but thermal resistance increases due to gap filling requirements
Solution Approach 1:
The diamond substrate undergoes preliminary thickness adjustment and surface preparation before being integrated into the CoWoS process flow. By pre-thinning edges and optimizing surface finish beforehand, the substrate can be directly integrated into standard packaging processes without requiring additional gap filling or extensive post-processing, thereby maintaining both process compatibility and thermal performance.
4Temperature
If diamond substrates are integrated, then heat spreading is improved, but warpage increases due to CTE mismatch with copper layers
Solution Approach 1:
The diamond substrate is designed with spatially varying properties: the central region maintains high thermal conductivity for heat spreading from the die attach area, while peripheral regions are thinned and potentially modified to reduce CTE mismatch effects with copper interconnect layers. This local differentiation allows the substrate to simultaneously provide excellent heat spreading where needed while minimizing warpage in regions where it interfaces with copper structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces thermal resistance and warpage, enabling efficient heat dissipation through direct jet impingement cooling, compatible with existing chip packaging flows, and maintains mechanical integrity without adding thermal resistance.
Implementation Method 1
diamond conducts heat very well and can serve as a heat spreader in electronics devices
Implementation Method 2
direct jet impingement cooling
Implementation Method 3
efficient heat dissipation through direct jet impingement cooling
Data Source
AI summary
A device package and heatsink assembly includes a device package containing one or more logic elements and one or more other integrated circuit devices mounted to a package substrate and one or more heatsinks. The other integrated circuit devices are higher above the package substrate's surface than the logic elements. Each heatsink contains chambers for a fluid heat transfer medium. A surface of the logic elements is thermally coupled to the fluid. A semiconductor chip package fabrication method includes bonding a diamond-containing dielet to a semiconductor logic die to form a logic die structure; mounting the logic die structure to a package substrate with the logic die sandwiched between the dielet and the substrate, exposing a surface of the dielet; and mounting one or more other integrated circuit devices to the package substrate. The other integrated circuit devices are higher above the package substrate's surface than the logic die structure.