DICE Register Input Hardening Against Single-Event Transients
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Solution Overview
Problem
Integrated circuits, particularly those with MOS transistor devices, are susceptible to destructive and nondestructive effects from ionizing radiation, leading to transient or persistent errors known as single-event upsets (SEUs). Existing radiation-hardening techniques, such as RHBP and RHBD, increase costs, power consumption, and circuit complexity while offering limited immunity to single-event transients.
Innovation Solution
The development of radiation-hardened registers that utilize resilient majority drivers and DICE flip-flops, combined with error-correction circuitry and glitch filters, to protect against single-event transients and static input errors. This solution employs triple-redundant input signals, digital majority voting, Muller C-elements for state retention, and analog majority voting to produce robust and reliable driver output signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If DICE flip-flops are used to harden storage cells against SEU, then reliability is improved, but device complexity and area increase
Solution Approach 1:
The register is divided into multiple independent DICE flip-flops, each handling a portion of the data. This segmentation allows the reliability improvement to be achieved through parallel independent units rather than complicating a single storage cell, managing complexity through modular organization.
Solution Approach 2:
The DICE flip-flop structure uses redundant copying of data across multiple transistors and storage nodes. Each bit is stored in a duplicated manner with interlocking feedback paths, creating inherent redundancy that provides SEU immunity without requiring external error correction complexity.
2Reliability
If triple-modular redundancy (TMR) is applied to enhance reliability, then reliability is improved, but area and power consumption increase
Solution Approach 1:
The patent combines TMR with DICE flip-flops in a hybrid architecture where the redundancy functions are merged. The triple-modular redundant DICE registers perform both the DICE interlocking function and the TMR majority voting function, eliminating the need for separate error detection and correction circuits, thus reducing overall area compared to implementing TMR and DICE separately.
Solution Approach 2:
The DICE flip-flop structure serves multiple functions simultaneously: it provides basic storage, SEU immunity through interlocking, and when triplicated, enables majority voting for TMR error correction. This multi-functionality reduces the need for additional dedicated error correction hardware, thereby reducing area overhead.
3Reliability
If DICE latch structure is used for spatial redundancy, then reliability is improved, but area and power consumption increase
Solution Approach 1:
The patent applies DICE structure selectively to storage elements that are most vulnerable to SEU, rather than uniformly hardening the entire circuit. By concentrating the redundant interlocking structure at critical storage nodes and using standard logic elsewhere, the power overhead is localized to where it provides maximum reliability benefit.
Solution Approach 2:
The DICE latch uses local copying of data within the latch structure itself through dual interlocked storage nodes. This local redundancy provides SEU immunity without requiring continuous refreshing or additional power-intensive error correction operations, as the interlocking feedback maintains data integrity passively.
4Reliability
If error-correction codes are implemented, then reliability is improved, but device complexity increases
Solution Approach 1:
The DICE flip-flop structure is self-correcting through its interlocking feedback mechanism. When a single-event upset flips a bit, the interlocked nature of the DICE structure detects the inconsistency and automatically restores the correct state without requiring external error correction logic, making the system self-service for error correction.
Solution Approach 2:
The DICE latch employs feedback paths that continuously monitor the state of storage nodes and provide corrective action through the interlocking structure. This inherent feedback mechanism provides error detection and correction functionality without requiring separate complex error-correction code implementation.
Data Source
AI summary
A resilient majority driver accepts triple-redundant input signals and provides a robust output signal unaffected by static errors on one of the input signals or by single-event transients caused by radiation within the driver. Data, clock, and asynchronous input signals to DICE (Dual Interlocked storage CEll) flip-flops in a register are driven by resilient majority drivers to construct an input-protected DICE register. Static errors are corrected using triple-redundant inputs and majority voting, while single-event strikes are largely corrected by the DICE architecture within each flip-flop and by the resilient majority drivers. Remaining errors in the input-protected DICE registers, such as those caused by single-event transients occurring during clock transitions, are corrected by error-correction encoders and decoders, whose output transients are suppressed by glitch filters. A resulting single-event effect tolerant register is more compact than a triple-redundant DICE register and requires no continuous external clock to correct errors.