Face-to-Back Die Bonding With Narrow Bond Pads to Prevent Shorting

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Solution Overview

Problem

The semiconductor industry faces challenges in integrating smaller and more creative packaging techniques for semiconductor dies due to the need for reducing feature sizes, which can lead to issues like shorting and pinhole defects, especially when bonding integrated circuit dies.

Innovation Solution

A die structure is formed by bonding integrated circuit dies in a face-to-back manner with bond pads having a lesser width than through-substrate vias, avoiding direct contact with semiconductor substrates and omitting recessing processes, thereby reducing shorting risks and pinhole defects.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If through-substrate vias are used to connect bonded dies, then vertical electrical connections are achieved, but the risk of shorting increases when bond pads contact semiconductor substrates

Engineering Contradiction:
Improveelectrical connection reliabilityVSAvoidshorting risk
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The through-substrate via is segmented into two distinct components: the via structure extending through the substrate and the bond pad formed on the via tip. This segmentation allows the bond pad to be electrically connected to the via while physically separated from the semiconductor substrate, preventing shorting while maintaining electrical connectivity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The bond pad acts as an intermediary element between the through-substrate via and the external bonding interface. It provides the necessary electrical connection while serving as a protective barrier that prevents direct contact between bonding wires and the semiconductor substrate, thereby eliminating shorting risks.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Manufacturing precision

If recessing processes are used to expose through-substrate vias, then via access is improved, but pinhole defects increase

Engineering Contradiction:
Improvevia access precisionVSAvoidpinhole defects
Core Design Contradiction:
Manufacturing precisionVSObject-generated harmful factors

Solution Approach 1:

The through-substrate vias are formed and extend completely through the semiconductor substrate before the bonding process. This preliminary formation ensures via access is already established, eliminating the need for subsequent recessing operations that would expose the vias and create pinhole defects.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

Instead of recessing the substrate to expose vias after bonding (the conventional approach), the invention inverts the sequence by forming complete through-vias before bonding. This reversal of the conventional process sequence eliminates the harmful recessing step while maintaining via accessibility.

Inventive Principle:
Principle #13The other way round (Inversion)

3Ease of manufacture

If bond pads have the same width as through-substrate vias, then manufacturing is simpler, but shorting risk increases due to potential contact with semiconductor substrates

Engineering Contradiction:
Improvebond pad fabrication simplicityVSAvoidshorting risk
Core Design Contradiction:
Ease of manufactureVSObject-affected harmful factors

Solution Approach 1:

The bond pad is designed with locally optimized dimensions that differ from the underlying via. Specifically, the bond pad width is controlled to be appropriate for external bonding while the via maintains its smaller diameter for electrical connection. This local quality differentiation prevents shorting while maintaining manufacturing feasibility.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS20260026407A1Die structures and methods of forming the same
Publication Date: 2026.01.22 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20260026407A1 patent drawing
  • US20260026407A1 patent drawing
  • US20260026407A1 patent drawing

AI summary

In an embodiment, a device includes: a first integrated circuit die comprising a semiconductor substrate and a first through-substrate via; a gap-fill dielectric around the first integrated circuit die, a surface of the gap-fill dielectric being substantially coplanar with an inactive surface of the semiconductor substrate and with a surface of the first through-substrate via; a dielectric layer on the surface of the gap-fill dielectric and the inactive surface of the semiconductor substrate; a first bond pad extending through the dielectric layer to contact the surface of the first through-substrate via, a width of the first bond pad being less than a width of the first through-substrate via; and a second integrated circuit die comprising a die connector bonded to the first bond pad.