Die-to-Die Bonding Via Layout for Lower Electrical Coupling
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Solution Overview
Problem
As semiconductor processing nodes advance, the reduced spacing between adjacent bonding pads on a semiconductor die leads to unwanted electrical coupling and performance degradation due to increased parasitic capacitance and other electrical effects.
Innovation Solution
The use of bonding vias with different sizes and shapes compared to bonding pads, along with a shielding grid, provides electrical isolation and increased spacing between bonding vias, reducing electrical coupling without additional shielding grids, and allowing for a simpler manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If bonding pads are placed closer together to increase density, then the number of bonding pads per unit area increases, but electrical coupling between adjacent bonding pads increases causing performance degradation
Solution Approach 1:
A shielding grid structure is introduced as an intermediary element between adjacent bonding pads. The shielding grid comprises conductive material arranged in a grid pattern that electrically isolates neighboring bonding pads from each other, thereby preventing unwanted electrical coupling while allowing the bonding pads to be placed closer together for increased density
Solution Approach 2:
The bonding pad structure is segmented into multiple components: individual bonding pads, shielding grids between them, and bonding vias. This segmentation allows each element to perform its specific function - bonding pads for electrical connection, shielding grids for isolation, and bonding vias for vertical interconnection - enabling high-density placement without electrical interference
2Object-affected harmful factors
If shielding grids are added between bonding pads to reduce electrical coupling, then electrical isolation improves, but manufacturing complexity increases
Solution Approach 1:
The shielding grid structure is merged with the existing bonding via formation process. The same dielectric layers and conductive material deposition steps used to create bonding vias are also used to form the shielding grid, combining multiple functions into a unified manufacturing sequence that reduces overall process complexity
Solution Approach 2:
The shielding grid serves multiple functions simultaneously: it provides electrical isolation between bonding pads, acts as a reference plane for signal integrity, and can be used as a grounding structure. This multi-functionality reduces the need for additional separate structures and simplifies the overall device design
3Object-affected harmful factors
If bonding vias are made smaller than bonding pads to increase spacing, then electrical coupling reduces, but bonding yield may be affected
Solution Approach 1:
Different sizes are assigned to different components based on their local requirements: bonding pads maintain larger dimensions to ensure reliable electrical connection and accommodate variation, while bonding vias are made smaller to increase spacing and reduce coupling. The shielding grid is positioned to compensate for the smaller via size, ensuring alignment tolerance does not compromise bonding yield
Data Source
AI summary
A semiconductor device is formed by bonding a first semiconductor die and a second semiconductor die at bonding pads in the first semiconductor die with bonding vias in the second semiconductor die, and by bonding dielectric layers in the first semiconductor die and in the second semiconductor die. Omitting bonding pads from the second semiconductor device, and instead using the bonding vias to bond the first and second semiconductor dies, provides a greater amount of spacing between the bonding vias of the second semiconductor die in that the bonding vias have lesser widths than bonding pads. This enables a greater amount of dielectric material of the dielectric layers of the second semiconductor device to be placed between the bonding vias without (or with minimally) increasing the lateral size of the second semiconductor die.