3D Die Layout Using Overlapped Bus and Metal Plate Capacitor
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Solution Overview
Problem
Existing chip layouts that include both a die and passive components occupy a large area, leading to low space utilization and high manufacturing costs, making compact design challenging.
Innovation Solution
The die layout is redesigned to integrate passive components, such as capacitors and inductors, within the die structure by overlapping bus signal boards and metal plates to form capacitors, optimizing area usage and reducing unnecessary components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If passive components are arranged separately from the die, then the circuit functionality is complete, but the area occupied increases and space utilization rate decreases
Solution Approach 1:
The patent merges the passive component with the die by integrating the capacitor formed between the bus signal board and metal plate directly into the die structure. The bus signal board and metal plate are arranged to overlap in the thickness direction, creating a capacitor that is both electrically functional and spatially compact, thus combining multiple functions (signal transmission and capacitance) into a single integrated structure.
Solution Approach 2:
The patent utilizes the thickness direction (vertical dimension) of the substrate to arrange the bus signal board and metal plate at different heights, allowing their projection regions to overlap on the substrate plane. This three-dimensional arrangement enables the capacitor to be formed without occupying additional horizontal area, effectively transitioning from a two-dimensional layout to a three-dimensional structure to improve space utilization.
2Area of stationary object
If passive components are integrated within the die, then space utilization rate improves, but manufacturing complexity increases
Solution Approach 1:
The metal plate serves multiple functions: it acts as an electrical connection element (pin) for the transistor and simultaneously forms one electrode of the capacitor when overlapping with the bus signal board. The bus signal board also serves dual purposes as a signal transmission pathway and as the other electrode of the capacitor. This multi-functionality reduces the need for separate dedicated capacitor structures, thereby simplifying the overall manufacturing process despite the integrated design.
3Area of stationary object
If the projection regions of bus signal board and metal plate overlap, then capacitor is formed with compact area, but manufacturing precision requirements increase
Solution Approach 1:
The patent employs a preliminary action by pre-defining the positions and dimensions of the bus signal board and metal plate during the die design and fabrication process. The overlapping arrangement is built-in from the outset, with the bus signal board and metal plate positioned to achieve the desired capacitor geometry before final assembly. This preliminary positioning ensures that the capacitor forms with the correct characteristics without requiring post-fabrication adjustment, thereby managing precision requirements through careful initial design.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances space utilization and reduces manufacturing costs by minimizing extra area occupation while improving the die's performance and efficiency.
Implementation Method 1
the first bus signal board and the first metal plate may jointly form a capacitor
Implementation Method 2
a dielectric layer is arranged between the first bus signal board and the first metal plate in the first direction
Data Source
Figure 1A~1B
Figure 2~3
Figure 4~5
AI summary
This application relates to the field of chip technologies, and discloses a die, a chip, and an electronic device. The die includes a substrate, and a first bus signal board, a first metal plate, and a transistor that are stacked on the substrate. The first bus signal board and the first metal plate are spaced apart in a first direction, and the first direction is a thickness direction of the substrate. In the first direction, a projection region of the first bus signal board on the substrate is a first projection region, a projection region of the first metal plate on the substrate is a second projection region, and the first projection region and the second projection region at least partially overlap. In the first direction, a projection region of the transistor on the substrate is a third projection region, and the third projection region and the first projection region are spaced apart from each other. The first bus signal board and the first metal plate are separately connected to pins of the transistor. A layout of a circuit inside the die is properly designed, thereby effectively improving a space utilization rate of the die, and reducing manufacturing costs.