Semiconductor Die Daisy-Chain RDL Coupling for Signal Integrity
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Solution Overview
Problem
3D memory devices face signal integrity degradation and increased power consumption due to the heavy load presented by stacked dies, which can lead to improper data latching and unacceptable performance in certain applications.
Innovation Solution
The use of a daisy chain coupling method through conductive structures and redistribution layers (RDL) with a 'U' shape, where terminals of semiconductor devices are connected to bond pads, reducing the load on external circuits and improving signal integrity by distributing the load serially rather than in parallel.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If stacked dies are coupled in parallel to external circuit, then memory capacity and bandwidth are increased, but signal integrity degrades and power consumption increases
Solution Approach 1:
The patent segments the parallel coupling approach into a daisy-chain serial coupling topology. Instead of connecting all dies simultaneously to the external circuit in parallel, the dies are connected sequentially through intermediate I/O circuits. This segmentation allows signals to be distributed one die at a time through the chain, reducing the simultaneous load on the external circuit while maintaining access to all dies, thus preserving signal integrity while supporting high memory capacity and bandwidth requirements.
2Quantity of substance
If stacked dies are coupled in parallel to external circuit, then memory capacity is increased, but load on external circuit increases
Solution Approach 1:
The patent divides the memory system into modular units where each die is accessed through intermediate I/O circuits in a daisy-chain configuration. This segmentation enables the external circuit to communicate with multiple dies sequentially rather than simultaneously, reducing the peak power consumption while maintaining the ability to access large total memory capacity across all dies in the stack.
3Device complexity
If stacked dies are coupled in parallel to external circuit, then signal distribution is simplified, but data latching becomes improper
Solution Approach 1:
The patent introduces intermediate I/O circuits as mediators between the external circuit and the stacked dies. These intermediary components buffer and condition signals before distributing them to individual dies through the daisy-chain topology. This mediation ensures that each die receives properly timed and conditioned signals, preventing improper data latching while managing the complexity of coupling multiple dies through sequential signal distribution rather than direct parallel connections.
Data Source
AI summary
Apparatuses and methods for coupling semiconductor devices are disclosed. Terminals (e.g., die pads) of a plurality of semiconductor devices may be coupled in a daisy chain manner through conductive structures that couple one or more terminals of a semiconductor device to two conductive bond pads. The conductive structures may be included in a redistribution layer (RDL) structure. The RDL structure may have a “U” shape in some embodiments of the disclosure. Each end of the “U” shape may be coupled to a respective one of the two conductive bond pads, and the terminal of the semiconductor device may be coupled to the RDL structure. The conductive bond pads of a semiconductor device may be coupled to conductive bond pads of other semiconductor devices by conductors (e.g., bond wires). As a result, the terminals of the semiconductor devices may be coupled in a daisy chain manner through the RDL structures, conductive bond pads, and conductors.