3D Die Interface Clock Alignment Using Controllable Delay Lines
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Solution Overview
Problem
In three-dimensional stacked semiconductor elements, data and clock signals experience misalignment during transmission due to signal delays, necessitating numerous delay strings that consume layout area and cause unnecessary power consumption.
Innovation Solution
A semiconductor device with controllable delay lines and clock generators on each die adjust clock signals to align phases, using phase detectors to generate phase relationship information for precise delay adjustments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a large number of delay strings are added to the data signal transmission path to adjust transmission phase, then the alignment between data signal and clock signal is improved, but the layout area consumption increases significantly
Solution Approach 1:
The patent replaces the mechanical/physical delay strings (which consume layout area) with a digital control system consisting of phase detectors and controllable delay elements. The phase detector detects phase differences between clock and data signals, and control signals adjust delay amounts digitally, eliminating the need for numerous physical delay strings and their associated layout area consumption.
Solution Approach 2:
The patent changes the delay parameter dynamically based on detected phase differences. Instead of using fixed physical delay strings, the system adjusts delay amounts through control signals that modify the delay parameter of delay elements, allowing precise alignment without consuming additional layout area.
2Manufacturing precision
If a large number of delay strings are disposed in the transmission path between different dies, then the transmission phase of data signal can be adjusted, but unnecessary power consumption is caused due to signal transition
Solution Approach 1:
The patent replaces passive delay strings that consume power during signal transitions with an active control system. The phase detector and controllable delay elements allow precise phase adjustment with minimal power consumption, as the delay is controlled digitally rather than through multiple signal transitions through delay strings.
Solution Approach 2:
The system automatically adjusts delay amounts based on phase detection feedback. The phase detector monitors the phase difference between clock and data signals and generates control signals that automatically adjust the delay elements, eliminating the need for manual configuration and reducing unnecessary power consumption from non-optimized delay strings.
3Manufacturing precision
If multiple delay strings are used to align clock and data signals, then signal alignment is achieved, but the working performance of semiconductor element is reduced
Solution Approach 1:
The patent replaces the bulky delay strings system with a compact digital control system that achieves the same alignment function with fewer components. This substitution reduces the impact on working performance by minimizing the number of signal paths and components that could interfere with normal semiconductor element operation.
Data Source
AI summary
An interface device includes a first controllable delay line (CDL), a first clock generator (CG), a phase detector (PD), a second CDL, and a second CG arranged on a second die. The first CDL delays a source clock signal of a first die to generate a first delayed clock signal. The first CG generates a second delayed clock signal according to the first delayed clock signal. The second CDL delays the source clock signal of the first die to generate a third delayed clock signal. The second CG generates a fourth delayed clock signal according to the third delayed clock signal. Based on a phase difference between a gained clock signal of the first die and the second delayed clock signal detected by the PD, the CDLs adjusts the delay amounts of the source clock signal.