Die Layout With Integrated Capacitor for Higher Chip Space Utilization

Solution Overview

Problem

Existing chip layouts that include both a die and passive components occupy a large area, leading to low space utilization and high manufacturing costs, making compact design challenging.

Innovation Solution

The layout of the circuit inside the die is redesigned to integrate passive components, such as capacitors and inductors, within the die structure, utilizing shared areas between bus signal boards and metal plates to form capacitors, and optimizing the arrangement of metal traces and source regions to reduce unnecessary space occupation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If passive components are arranged separately from the die, then the chip can meet use requirements in different scenarios, but the area occupied increases and space utilization rate decreases

Engineering Contradiction:

Improveuse requirements in different scenariosVSAvoidarea occupied by chip

Core Design Contradiction:

Adaptability or versatilityVSArea of stationary object

Solution Approach 1:

The patent merges the passive component with the die structure by integrating the capacitor between the bus signal board and the metal plate that are already part of the die. This combining approach eliminates the need for separate passive component areas while maintaining the required capacitance function for impedance adjustment in different scenarios.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The metal plate in the die serves dual functions: it acts as an electrical connection element and simultaneously forms a capacitor with the bus signal board. This multi-functionality allows the same structure to provide both connectivity and passive component functionality, reducing overall chip area while maintaining versatility.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Adaptability or versatility

If passive components are arranged separately from the die, then the chip can meet use requirements in different scenarios, but the space utilization rate decreases

Engineering Contradiction:

Improveuse requirements in different scenariosVSAvoidspace utilization rate

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent merges the passive component with the die structure by integrating the capacitor between the bus signal board and the metal plate that are already part of the die. This combining approach eliminates the need for separate passive component areas while maintaining the required capacitance function for impedance adjustment in different scenarios.

Inventive Principle:

Principle #5Merging (Combining)

3Adaptability or versatility

If passive components are arranged separately from the die, then the chip can meet use requirements in different scenarios, but manufacturing costs increase

Engineering Contradiction:

Improveuse requirements in different scenariosVSAvoidmanufacturing costs

Core Design Contradiction:

Adaptability or versatilityVSEase of manufacture

Solution Approach 1:

The patent merges the passive component with the die structure by integrating the capacitor between the bus signal board and the metal plate that are already part of the die. This combining approach eliminates the need for separate passive component areas while maintaining the required capacitance function for impedance adjustment in different scenarios.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The metal plate in the die serves dual functions: it acts as an electrical connection element and simultaneously forms a capacitor with the bus signal board. This multi-functionality allows the same structure to provide both connectivity and passive component functionality, reducing overall chip area while maintaining versatility.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances space utilization and reduces manufacturing costs by minimizing extra area usage and parasitic inductance, improving the performance and efficiency of the chip.

Implementation Method 1

the first bus signal board and the first metal plate may jointly form a capacitor

Methodology Applied

Scientific EffectCapacitance: Capacitance

Implementation Method 2

a dielectric layer is arranged between the first bus signal board and the first metal plate in the first direction

Methodology Applied

Scientific EffectDielectric: Dielectric

Data Source

PatentUS20260068686A1Die, chip, and electronic device

Publication Date: 2026.03.05 HUAWEI TECH CO LTD

AI summary

A die includes a substrate, a first bus signal board, a first metal plate, and a transistor that are stacked on the substrate. The first bus signal board and the first metal plate are spaced apart in a first direction which is a thickness direction of the substrate. In the first direction, a projection region of the first bus signal board on the substrate is a first projection region, a projection region of the first metal plate is a second projection region, and the first projection region and the second projection region at least partially overlap; a projection region of the transistor on the substrate is a third projection region, and the third projection region and the first projection region are spaced apart from each other. The first bus signal board and the first metal plate are separately connected to pins of the transistor.