Die-Level Transistor Parameter Extraction from Logic Block Measurements
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Solution Overview
Problem
Wafer-level testing in IC fabrication fails to provide die-level electrical parameters for each die, as the number of test sites is insufficient to offer detailed measurements for the numerous dies on a wafer, necessitating a method to extract die-level electrical parameters from logic block measurements.
Innovation Solution
A method and apparatus that estimate a mapping relationship between transistor types' electrical parameters and logic blocks' measurement results, using a processor and machine-readable medium to obtain and generate die-level electrical parameters through matrix multiplication and AI modeling, enabling accurate extraction without additional testing patterns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If wafer-level testing is performed with a predetermined WAT model specifying a number of test sites, then wafer acceptance testing can be completed, but the number of test sites is much smaller than the number of dies fabricated, resulting in inability to provide die-level electrical parameters for each die
Solution Approach 1:
The patent creates a virtual copy of die-level electrical parameters by establishing a mapping relationship between WAT measurement results and transistor electrical parameters. Instead of directly measuring each die, the system copies the measurement pattern from a limited number of WAT sites and uses AI modeling to generate estimated electrical parameters for all dies on the wafer, thereby obtaining die-level information without requiring die-level physical measurements
Solution Approach 2:
The patent introduces an intermediary mapping relationship and AI model between WAT measurement results and transistor electrical parameters. This intermediary layer enables the transformation of coarse-grained WAT measurement data into fine-grained die-level electrical parameter estimates, bridging the gap between the limited test sites and the numerous dies without requiring direct measurement of each die
2Measurement precision
If the number of WAT sites is increased to provide die-level electrical parameters for each die, then measurement coverage improves, but testing time and cost increase significantly
Solution Approach 1:
The patent applies partial action by performing measurements on only a limited number of WAT sites rather than all dies, yet through the mapping relationship and AI modeling, achieves comprehensive die-level electrical parameter extraction for the entire wafer. This partial measurement approach significantly reduces testing time while maintaining die-level parameter availability through computational estimation
3Measurement precision
If die-level electrical parameters are extracted through traditional chip probing methods, then accurate measurements can be obtained, but additional testing processes and costs are incurred
Solution Approach 1:
The patent makes the WAT measurement system universal by enabling it to serve dual purposes: traditional wafer acceptance testing and die-level electrical parameter extraction. By establishing a mapping relationship between WAT measurements and transistor parameters, the same WAT infrastructure is used to achieve both functions, eliminating the need for separate chip probing processes and reducing overall testing complexity
Data Source
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AI summary
A die-level electrical parameter extraction method includes: obtaining electrical parameters of a plurality of transistor types; obtaining measurement results of a plurality of logic blocks; estimating a mapping relationship between the electrical parameters of the plurality of transistor types and the measurement results of the plurality of logic blocks; and regarding a specific die of a wafer, obtaining die-level measurement of the plurality of logic blocks, and generating die-level electrical parameters of the plurality of transistor types according to the mapping relationship and the die-level measurement results.