Die Package Collapse Control for TCB Warpage Mitigation
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Solution Overview
Problem
The use of thick die backside layers with high thermal conductivity in IC packaging leads to die warpage during thermal compression bonding (TCB) due to coefficient of thermal expansion (CTE) mismatch, causing solder bridging and joint opens, which are assembly failures.
Innovation Solution
Incorporation of collapse control features, patterned die backside layers, and non-uniform interconnect structures to mitigate warpage, including support features on the substrate and openings/grooves in the die backside layer, as well as varying solder bump heights and widths to accommodate thermal expansion differences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If thicker die backside layers are used to improve heat dissipation and warpage control during surface mounting, then thermal conductivity and warpage control are improved, but die warpage during thermal compression bonding worsens due to CTE mismatch
Solution Approach 1:
The patent applies local quality by creating non-uniform interconnect structures with varying heights across the die surface. Central regions have taller interconnect structures while peripheral regions have shorter ones, compensating for the warpage induced by thick die backside layers during TCB. This localized structural variation allows the die to maintain proper contact with the substrate despite thermal expansion differences.
Solution Approach 2:
The patent employs asymmetry by designing interconnect structures with different heights in different regions of the die. The asymmetric height distribution (taller in center, shorter at edges) counteracts the symmetric warpage tendency caused by uniform thermal expansion of the thick die backside layer, enabling successful bonding without excessive warpage.
2Temperature
If thicker die backside layers are used to improve heat dissipation, then thermal management is improved, but solder bridging at die corners worsens due to excessive warpage
Solution Approach 1:
The patent addresses solder bridging by implementing local quality through varied interconnect heights. Peripheral regions with shorter interconnect structures prevent excessive solder accumulation at die corners during bonding, while central regions with taller structures maintain proper solder joints. This localized differentiation eliminates the uniform warpage that causes solder bridging.
3Stability of the object's composition
If thicker die backside layers are used to improve warpage control during surface mounting, then package stability is improved, but joint opens at die center regions worsen due to warpage
Solution Approach 1:
The patent resolves joint opens by applying local quality through centrally-located taller interconnect structures. These elevated central interconnects ensure continuous electrical and mechanical contact between the die center and substrate during bonding, preventing joint opens even when the thick die backside layer causes warpage. The localized height variation compensates for thermal expansion differences at the die center.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Reduces die warpage and assembly failures by preventing solder bridging and joint opens, improving assembly yield and product performance.
Implementation Method 1
Die back side layers, either metallic or composite, may exhibit high thermal conductivities and thus can benefit package heat dissipation
Implementation Method 2
the die backside layers may possess a coefficient of thermal expansion (CTE) that is larger than that of silicon. This CTE mismatch can result in die warpage during TCB
Data Source
AI summary
Microelectronic die package structures formed according to some embodiments may include a substrate comprising one or more conductive interconnect structures on a surface of the substrate. One or more support features are on one or more peripheral regions of the surface of the substrate. A first side of a die is coupled to the one or more conductive interconnect structures and is over the one or more support features. A die backside layer is on the second side of the die.