Die-to-Die PLL Clock Alignment for Low-Latency High-Bandwidth Links

The patent merges system-synchronous and source-synchronous clock distribution approaches into a hybrid architecture. The system-synchronous PLL provides a common reference clock across all dies to establish a unified time base, while source-synchronous delay circuits are integrated at each die to locally adjust for timing skew. This combination allows data and clock signals to be launched simultaneously from each die while maintaining global synchronization, thereby reducing latency and increasing bit rate compared to traditional asynchronous approaches.

The patent extracts the synchronization function from separate buffering circuits and integrates it directly into the clock distribution and data launch path. By using PLLs to generate synchronized clock signals and delay circuits to adjust timing at the source, the need for additional buffering circuits is eliminated. This integration maintains data transfer reliability through precise timing control while reducing device complexity and power consumption.

The patent introduces PLL circuits as intermediary devices at each die that generate local clock signals based on a reference clock received from other dies. This intermediary mechanism allows each die to independently generate synchronized clock signals despite physical separation, compensating for propagation delays through local phase adjustment. The delay circuits act as additional intermediaries to fine-tune timing, enabling high integration density through advanced packaging while maintaining low latency through active synchronization.