Semiconductor Package Sidewall Stress Relief for Warpage Reduction
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Solution Overview
Problem
Integrated circuit packages experience stress-induced warpage due to material differences, leading to non-bond issues and circuit failures.
Innovation Solution
A stress relief layer with low Young's modulus and density is formed on the sidewalls of package components, which absorbs and buffers stress from encapsulants, while also protecting low-k dielectric layers from moisture.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If package components are bonded together to increase functionality and integration level, then the functionality and integration level are improved, but stress occurs due to material differences causing warpage
Solution Approach 1:
A stress relief layer is introduced as an intermediary component between the encapsulant and the package components (die and substrate). This stress relief layer has a Young's modulus lower than both the encapsulant and the package components, allowing it to absorb and distribute stress uniformly, preventing warpage while maintaining the bonded structure's functionality.
Solution Approach 2:
The stress relief layer is designed with specific material parameters (Young's modulus lower than encapsulant and package components, and density lower than encapsulant) to optimize its stress-absorbing capability. By carefully selecting and controlling these physical parameters, the layer effectively mitigates stress-induced warpage without compromising the bonded structure's integrity.
2Stability of the object's composition
If stress relief layer with low Young's modulus and density is formed, then stress-related warpage is reduced, but device complexity increases
Solution Approach 1:
The stress relief layer is segmented to extend only into the gaps between adjacent packaged components rather than covering the entire package surface. This selective placement reduces the amount of material required and simplifies the overall structure while still effectively relieving stress at the critical interfaces where warpage occurs.
Solution Approach 2:
The stress relief layer is applied locally only where needed - specifically in the gap regions between packaged components - rather than uniformly across the entire package. This localized application optimizes stress relief performance while minimizing added complexity and material usage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The stress relief layer effectively reduces stress-related warpage and prevents moisture ingress, enhancing bonding integrity and reliability of integrated circuit packages.
Implementation Method 1
The stress relief layer may have a low Young's modulus and a low density, so that it may relieve some stress applied by an encapsulant (gap-filling material) subsequently formed thereon
Implementation Method 2
A stress relief layer is formed on the sidewall of the top wafer and extends on some parts of the top surface of the bottom die
Data Source
AI summary
A method includes bonding a top die over a bottom wafer, depositing a stress relief layer on the top die and a top surface of the bottom wafer, forming a dielectric gap-filling layer on the stress relief layer, performing a planarization process on the dielectric gap-filling layer, and sawing the dielectric gap-filling layer and the bottom wafer to form a plurality of packages. One of the packages includes the top die, a portion of the stress relief layer, and a bottom die in the bottom wafer.