Die-Stacked Device Partitioned Multi-Hop Network Scalability
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Solution Overview
Problem
Conventional horizontal-stacked processing systems face scalability issues due to increased cost, complexity, and power consumption as the number of dies grows, as they require more metal layers or longer interconnects for point-to-point communication, which does not scale effectively.
Innovation Solution
Implementing a multi-hop communication network with a partitioned router and link partition, where the router partition is distributed across the die and the link partition is implemented in the interposer's metal layers and intra/inter-die interconnects, allowing for scalable communication without the need for excessive metal layers or long interconnects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If point-to-point links are used to provide communication between horizontally-stacked die, then communication between pairs of die is enabled, but the system does not scale with the number of die and requires an increase in the number of metal layers in the interposer, which significantly increases cost and complexity
Solution Approach 1:
The patent introduces a network interface as an intermediary component that enables multi-hop communication between dies. Instead of requiring direct point-to-point links between all pairs of dies, the network interface acts as a mediator that routes communications through intermediate nodes, allowing the system to scale without proportionally increasing the number of metal layers.
Solution Approach 2:
The patent transitions from a two-dimensional point-to-point linking approach to a multi-dimensional network topology. By organizing dies in a network with multiple hops and intermediate routing nodes, the communication architecture moves beyond direct pairwise connections to a more scalable dimensional structure that reduces the growth rate of required metal layers.
2Productivity
If the number of die in a conventional horizontal-stacked system is increased, then processing capacity is improved, but either the number of metal layers in the interposer must increase (significantly increasing cost and complexity) or the lengths of certain traces of the interposer must increase (significantly increasing power consumption, signal latency, and skew mismatch)
Solution Approach 1:
The patent segments the communication path into multiple shorter hops through the introduction of network interfaces on intermediate dies. Instead of requiring single long traces to connect distant dies directly, the communication is divided into multiple shorter segments that can be routed through intermediate nodes, reducing the length of individual traces and associated power consumption.
3Device complexity
If the lengths of certain traces of the interposer are increased to accommodate more die, then the number of metal layers can be maintained, but power consumption, signal latency, and skew mismatch are significantly increased
Solution Approach 1:
The network interface acts as an intermediary that breaks up long communication paths into shorter segments. By introducing intermediate routing points on other dies, the system maintains shorter trace lengths and reduces signal latency, even as the overall system scales to accommodate more die without increasing metal layer count.
Data Source
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AI summary
An electronic assembly (100) includes horizontally-stacked die (104, 105, 106, 107) disposed at an interposer (102), and may also include vertically-stacked die (107, 111, 112, 113). The stacked die are interconnected via a multi-hop communication network (101) that is partitioned into a link partition and a router partition. The link partition is at least partially implemented in the metal layers of the interposer for horizontally-stacked die. The link partition may also be implemented in part by the intra-die interconnects (334, 335) in a single die and by the inter-die interconnects (222) connecting vertically-stacked sets of die. The router partition is implemented at some or all of the die disposed at the interposer and comprises the logic (402, 404, 406, 408) that supports the functions that route packets among the components of the processing system (100) via the interconnects of the link partition. The router partition may implement fixed routing, or alternatively may be configurable using programmable routing tables (406) or configurable logic blocks.