Die Substrate Edge Plating for Power Delivery and Signal Routing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The increasing demand for higher memory bandwidth and higher current in semiconductor applications, such as Graphics Processing Clusters and Texture Processing Clusters, necessitates larger and denser ball grid arrays (BGAs) on die substrates, which strain printed circuit board design and require more efficient current conduction solutions.
Innovation Solution
The die substrate design reroutes current and ground connections to the edge of the die substrate via a termination layer and electrically conductive plating, reducing the need for solder balls on the underside and allowing for increased current conduction and signal routing capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If larger and denser ball grid arrays (BGAs) are used to provide higher current demand, then current conduction capability is improved, but the burden on printed circuit board design layout increases and space for signal routing is reduced
Solution Approach 1:
The patent routes current-carrying metal lines to the body edge surfaces of the dielectric body, moving current conduction from the traditional bottom BGA area to the lateral edges. This dimensional transition allows current paths to occupy peripheral regions while freeing central areas for signal routing, effectively resolving the space conflict between power delivery and signal integrity
Solution Approach 2:
The patent segments the electrical connection functions by separating current-carrying lines from signal-carrying lines. Current lines are routed to edge surfaces with termination layers and conductive plating, while signal lines maintain access to the bottom surface. This functional segmentation allows independent optimization of power delivery and signal routing without mutual interference
2Power
If more solder balls are used to increase BGA density for higher current demand, then current conduction is improved, but PCB design layout complexity increases
Solution Approach 1:
The patent extracts the current conduction function from the traditional BGA solder ball array and relocates it to edge-mounted termination layers and conductive plating. This extraction eliminates the need for dense solder ball arrangements dedicated to power delivery, thereby simplifying PCB layout while maintaining high current capability through alternative edge-based connection structures
3Area of stationary object
If current-carrying metal lines are routed to body edge surfaces, then space for signal routing is freed up, but additional termination layers and conductive plating are required
Solution Approach 1:
The patent merges the termination layer and conductive plating into an integrated edge-connection system. The termination layer provides electrical termination at the edge, while the conductive plating extends connectivity to external components. This merging creates a unified edge-based interface that accomplishes both current conduction and external connectivity without requiring separate complex subsystems
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances current conduction and frees up space for signal routing, supporting higher memory bandwidth applications and improving decoupling effects by locating capacitors closer to the die.
Implementation Method 1
an electrically conductive plating located on the at least one body edge surface and connected to the termination layer for an electrical current connection
Data Source
AI summary
A die substrate, including a dielectric body, the body having a first body surface, a second body surface on an opposite side and body edge surfaces located in between. Current-carrying metal lines located in the dielectric body. One or more of the metal lines routed to one or more of the body edge surfaces. A termination layer located on the at least one body edge surface and electrically connected to the least one of the metal lines routed to the body edge surfaces. Electrically conductive plating located on the at least one body edge surface. The plating connected to the termination layer for an electrical current connection or a ground connection to the at least one metal line. A method of manufacturing an integrated circuit package, the package and a computer having the die substrate are also disclosed.