Dielectric Blocking Layer for Memory Device Reliability

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Solution Overview

Problem

Memory devices are susceptible to interpoly dielectric breakdown and memory device dielectric breakdown during implantation steps, and non-selective silicidation can cause shorts between memory devices and adjacent stacks, requiring additional masks to prevent these issues.

Innovation Solution

A method involving the formation of a dielectric blocking layer and selective silicidation, where a conformal insulating layer and polysilicon layer are formed over a memory stack, followed by a dielectric blocking layer to prevent implantation and silicidation, ensuring uniformity and preventing shorts between memory devices.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If additional masks are used to prevent silicidation on memory devices, then silicidation-related shorts are prevented, but device complexity and manufacturing cost increase

Engineering Contradiction:
Improveprevention of silicidation shortsVSAvoidnumber of masks required
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

A conformal insulating layer is formed over the sidewalls and upper surface of the memory stack before any silicidation processes. This preliminary protective layer prevents silicidation from occurring on the memory device, eliminating the need for additional masks to block silicidation while maintaining reliability

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The conformal insulating layer acts as an intermediary barrier between the silicidation process and the memory device. This intermediate layer selectively protects the memory device from silicidation while allowing silicidation to proceed on adjacent memory stacks, thereby preventing shorts without requiring complex mask structures

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If implantation steps are performed on memory devices, then memory device functionality is achieved, but interpoly dielectric breakdown and dielectric breakdown occur

Engineering Contradiction:
Improvememory device functionalityVSAvoiddielectric breakdown during implantation
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The conformal insulating layer is formed over the memory stack before implantation steps. This preliminary protective layer shields the dielectric structures from damage during subsequent implantation processes, preventing interpoly dielectric breakdown and memory device dielectric breakdown while allowing the implantation to proceed for memory device formation

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The conformal insulating layer serves as a cushioning protective barrier that absorbs or mitigates the harmful effects of implantation on the dielectric structures. By providing this protective cushion before implantation, the layer prevents dielectric breakdown without interfering with the memory device functionality that requires implantation

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances the reliability and uniformity of memory devices by preventing interpoly dielectric breakdown, dielectric breakdown, and silicidation-related shorts, while eliminating the need for additional masks, resulting in a cost-effective and highly reliable memory device.

Implementation Method 1

Memory devices are susceptible to interpoly dielectric breakdown and memory device dielectric breakdown during implantation steps

Methodology Applied
Scientific EffectIon Implantation: Ion Implantation

Implementation Method 2

additional masks are often required to prevent silicidation on the memory device, which can cause shorts between the memory device and an adjacent memory stack

Methodology Applied
Scientific EffectSilicidation:

Data Source

PatentUS11158646B2Memory device with dielectric blocking layer for improving interpoly dielectric breakdown
Publication Date: 2021.10.26 GLOBALFOUNDRIES SINGAPORE PTE LTD
  • US11158646B2 patent drawing
  • US11158646B2 patent drawing
  • US11158646B2 patent drawing

AI summary

A memory device with a dielectric blocking layer for improving interpoly dielectric breakdown is provided. Embodiments include.