Dielectric Bonding Pattern Definition Layer for Semiconductor Wafer Alignment
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Solution Overview
Problem
Hybrid wafer-to-wafer bonding in semiconductor devices faces challenges with poor overlay tolerance, leading to smaller conductive bonding pads, non-planar die bonding surfaces, and yield losses due to dielectric erosion after chemical mechanical polishing, resulting in a suboptimal conductive pad density to dielectric material density ratio.
Innovation Solution
A dielectric bonding pattern definition layer with bonding pattern definition openings is introduced between semiconductor dies, allowing for improved overlay tolerance, increased bonding pad size and density, reduced erosion, and simplified planarization, while preventing short circuits through insulation between adjacent bonding interfaces.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If hybrid wafer-to-wafer bonding is performed without a dielectric bonding pattern definition layer, then bonding pad size is reduced, but overlay tolerance deteriorates and manufacturing precision decreases
Solution Approach 1:
A dielectric bonding pattern definition layer is introduced as an intermediary between the bonding pads of opposing dies. This layer contains openings that define the bonding pattern and guide the alignment process, serving as a mediator that improves overlay tolerance while allowing for larger bonding pad areas. The dielectric layer acts as a reference structure that facilitates precise alignment without constraining the bonding pad dimensions.
2Quantity of substance
If bonding pad density is increased without a dielectric bonding pattern definition layer, then conductive pad density to dielectric material density ratio improves, but dielectric erosion during chemical mechanical polishing increases
Solution Approach 1:
The dielectric bonding pattern definition layer is formed in advance before the bonding process and chemical mechanical polishing. This preliminary structure defines the bonding pattern openings that protect the underlying dielectric material during polishing, preventing erosion while allowing increased bonding pad density. The pre-formed dielectric layer with defined openings serves as a protective template throughout the subsequent processing steps.
3Reliability
If bonding pad size is increased to improve bonding strength, then bonding reliability improves, but die bonding surface planarity deteriorates
Solution Approach 1:
The bonding interface is segmented into distinct regions: bonding pad center regions that protrude through dielectric openings for bonding, and peripheral regions that remain covered by dielectric material. This segmentation allows larger bonding pads to be used for improved bonding strength while the dielectric material in peripheral regions maintains surface planarity. The openings create discrete bonding zones that preserve overall surface flatness.
Data Source
AI summary
A bonded assembly and a method of forming a bonded assembly includes providing a first semiconductor die including a first substrate, first semiconductor devices, and first bonding pads that are electrically connected to a respective node of the first semiconductor devices, providing a second semiconductor die including a second substrate, second semiconductor devices, and second bonding pads that are electrically connected to a respective node of the second semiconductor devices, forming a dielectric bonding pattern definition layer including bonding pattern definition openings therethrough over the second bonding pads, and bonding the second bonding pads to the first bonding pads, where the first metal pads expand through the bonding pattern definition openings and are bonded to a respective one of the second bonding pads.