Dielectric Fin eFuse Cell Layout for Higher OTP Memory Density
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Solution Overview
Problem
The challenge of integrating one-time-programmable (OTP) memory devices, such as efuse devices, into advanced integrated circuits is exacerbated by the mismatch in size reduction rates between transistor features and efuse components, leading to increased real estate requirements that hinder integration as circuit technology advances.
Innovation Solution
The efuse cells are designed with a fork configuration where a dielectric fin structure is interposed between nanostructures acting as channels for sub-transistors, reducing the area required for each efuse cell and allowing more cells to be integrated in a given space by forming access transistors in parallel.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If efuse cells are designed with traditional configurations, then the device functionality is maintained, but the area occupied by each efuse cell is large, hindering integration into advanced circuits
Solution Approach 1:
The patent introduces a dielectric fin structure that extends vertically from the substrate, utilizing the vertical dimension to reduce the horizontal footprint of each efuse cell. By stacking functional layers (semiconductor fins, gate structures, interconnects) vertically around and along the dielectric fin, the design achieves three-dimensional integration that packs more functionality into a smaller planar area, directly addressing the area reduction goal while maintaining device functionality
Solution Approach 2:
The patent implements a nested structure where multiple functional components are arranged concentrically around the central dielectric fin. The semiconductor fins are positioned adjacent to the dielectric fin, gate structures wrap around the semiconductor fins, and interconnect structures are layered above. This nested arrangement allows efficient space utilization where each component is positioned to minimize overall cell area while maintaining electrical functionality, effectively reducing the area occupied by each efuse cell
2Length of moving object
If transistor features are scaled down to match circuit technology advances, then integration density is improved, but efuse components do not scale at the same rate, leading to mismatched size reduction
Solution Approach 1:
The patent changes the geometric parameters of the efuse cell structure by introducing a vertical dielectric fin and arranging components in a three-dimensional configuration. This structural parameter change allows the efuse cell to scale more effectively with transistor dimensions, as the vertical extent of the dielectric fin and surrounding components can be proportionally reduced alongside transistor feature sizes, achieving better size matching precision across different technology nodes
Solution Approach 2:
By transitioning from a planar to a three-dimensional structure with vertical dielectric fins and stacked layers, the patent enables efuse components to scale more effectively with transistor dimensions. The vertical dimension provides additional scaling freedom, allowing the horizontal footprint to be reduced proportionally with transistor features while maintaining functional dimensions through vertical stacking, thus achieving matched size reduction rates
3Quantity of substance
If more efuse cells are integrated in a given space, then the memory capacity is increased, but the area required for each cell must be reduced
Solution Approach 1:
The patent utilizes vertical stacking of functional layers around dielectric fins to reduce the planar footprint of each efuse cell. By arranging semiconductor fins, gate structures, and interconnects in vertical layers rather than spreading them out horizontally, the design achieves higher cell density in a given area, enabling more efuse cells to be integrated while maintaining adequate spacing for manufacturing and electrical isolation
Solution Approach 2:
The patent merges multiple functional components into a compact integrated structure centered around each dielectric fin. The semiconductor fins, gate structures, and interconnect elements are combined in a shared vertical space around the dielectric fin, eliminating the need for separate planar regions for each component. This merging approach reduces the total area per cell while maintaining all necessary functions, enabling higher integration of efuse cells in the given space
Data Source
AI summary
A semiconductor device includes a plurality of first nanostructures extending along a first lateral direction. The semiconductor device includes a first epitaxial structure and second epitaxial structure respectively coupled to ends of each of the plurality of first nanostructures along the first lateral direction. The semiconductor device includes a dielectric fin structure disposed immediately next to a sidewall of each of the plurality of first nanostructures facing a second lateral direction perpendicular to the first lateral direction. The semiconductor device includes a first gate structure wrapping around each of the plurality of first nanostructures except for the sidewalls of the first nanostructures. The semiconductor device includes a metal structure disposed above the first gate structure and coupled to one of the first or second epitaxial structure.