Dielectric Isolation Fin With Helmet Structure for MBC Transistors
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Solution Overview
Problem
Existing dielectric isolation structures in semiconductor integrated circuits (ICs) are inadequate for preventing undesirable electrical connections between adjacent source/drain features, particularly in multi-gate devices like MBC transistors.
Innovation Solution
A dielectric fin structure with a helmet feature is introduced, featuring a tapered profile with a larger top width and a smaller bottom width. This design facilitates source/drain feature patterning and gate formation while minimizing parasitic capacitance by not overly extending the helmet feature into the low-k base feature.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing dielectric isolation structures are used, then source/drain features can be isolated, but adjacent source/drain features may merge resulting in undesirable electrical connections
Solution Approach 1:
The dielectric isolation structure is segmented into multiple functional regions: a base dielectric region providing primary isolation, and a helmet dielectric region extending over the channel region to provide enhanced isolation at critical interfaces. This segmentation allows each region to optimize its function, preventing source/drain merging while maintaining manufacturing feasibility.
Solution Approach 2:
The isolation structure extends into the vertical dimension with the helmet dielectric region rising above the base dielectric level. This three-dimensional configuration provides superior isolation coverage without increasing lateral dimensions, effectively preventing source/drain feature merging while maintaining compact device geometry.
2Reliability
If dielectric fins are used to isolate source/drain features, then electrical connections are prevented, but parasitic capacitance increases
Solution Approach 1:
The helmet dielectric region is strategically positioned only where needed - extending over the channel region and adjacent to the gate structure where isolation is most critical. The base dielectric material has lower permittivity than the helmet dielectric, creating local quality variations that reduce parasitic capacitance in regions where it matters least while maintaining strong isolation where required.
Solution Approach 2:
The isolation structure combines two dielectric materials with different properties: a base dielectric with lower permittivity for reducing parasitic capacitance, and a helmet dielectric with higher permittivity for providing robust isolation at critical interfaces. This composite approach balances isolation effectiveness with parasitic capacitance reduction.
3Reliability
If helmet feature extends deeply into base feature, then isolation is enhanced, but parasitic capacitance increases due to low-k base feature displacement
Solution Approach 1:
The helmet dielectric region is designed with optimized dimensions - extending a controlled distance into the base dielectric region rather than fully replacing it. This parameter optimization ensures sufficient isolation strength while maintaining enough low-k base dielectric material to limit parasitic capacitance increases. The extent of helmet penetration is carefully controlled as a design parameter.
Data Source
AI summary
Semiconductor structures and methods of forming the same are provided. A method according to the present disclosure includes forming a stack of epitaxial layers over a substrate, forming a first fin-like structure and a second fin-like structure from the stack, forming an isolation feature between the first fin-like structure and the second fin-like structure, forming a cladding layer over the first fin-like structure and the second fin-like structure, conformally depositing a first dielectric layer over the cladding layer, depositing a second dielectric layer over the first dielectric layer, planarizing the first dielectric layer and the second dielectric layer until the cladding layer are exposed, performing an etch process to etch the second dielectric layer to form a helmet recess, performing a trimming process to trim the first dielectric layer to widen the helmet recess, and depositing a helmet feature in the widened helmet recess.