Dielectric Fin Isolation for Uniform FinFET Metal Gate Formation
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Solution Overview
Problem
As integrated circuits (ICs) continue to scale down, isolating adjacent metal gate electrodes and source/drain electrodes becomes increasingly complex, leading to challenges in uniform metal gate formation and accidental merging of source/drain features, which affects the performance and reliability of transistors.
Innovation Solution
The use of dielectric fins with a jogged shape, where the fins are narrower between metal gates than between source/drain features, provides improved isolation and room for uniform metal gate formation, utilizing a mix of low-k and high-k layers for etch selectivity and reduced coupling capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional isolation structures are used to isolate adjacent metal gate electrodes and source/drain electrodes, then isolation is achieved, but manufacturing complexity increases and uniform metal gate formation becomes difficult
Solution Approach 1:
The isolation structure is segmented into dielectric fins positioned between adjacent metal gate electrodes and source/drain electrodes. Each dielectric fin acts as an independent isolation element, providing localized isolation where needed while maintaining open spaces in other regions. This segmentation allows for simplified manufacturing compared to continuous isolation structures.
Solution Approach 2:
The dielectric fins provide localized isolation quality precisely where adjacent electrodes need to be separated. The isolation is concentrated at specific locations (between gates and between source/drain) rather than applied uniformly across the entire structure. This local quality approach reduces overall manufacturing complexity while maintaining necessary isolation.
2Reliability
If conventional isolation structures are used, then isolation is provided, but uniform metal gate formation becomes difficult
Solution Approach 1:
By segmenting the isolation into discrete dielectric fins rather than continuous structures, the patent creates defined open spaces between isolation elements. These open spaces allow metal gate forming materials to be deposited uniformly across the substrate without being disrupted by continuous isolation structures, thereby improving metal gate uniformity while maintaining isolation effectiveness.
Solution Approach 2:
The isolation structure transitions from a planar, two-dimensional approach to a three-dimensional vertical fin structure. The dielectric fins extend vertically between the substrate and upper layers, providing isolation in the vertical dimension while leaving horizontal spaces open for uniform metal gate formation. This dimensional change resolves the conflict between isolation and gate uniformity.
3Productivity
If IC dimensions are reduced to improve production efficiency, then production efficiency increases, but complexity of manufacturing processes increases
Solution Approach 1:
The segmented dielectric fin structure allows for scalable manufacturing that can adapt to reduced IC dimensions. As features are scaled down, the fin-based isolation can be proportionally reduced while maintaining its functional effectiveness. The modular nature of discrete fins makes them easier to manufacture at smaller scales compared to continuous isolation structures, thereby supporting production efficiency improvements without proportionally increasing complexity.
Data Source
AI summary
A method includes providing a structure having two fins extending from a substrate; an isolation structure isolating bottom portions of the fins; source/drain (S/D) features over each of the fins; a dielectric fin oriented lengthwise parallel to the fins and disposed between the two fins and over the isolation structure; a dummy gate stack over the isolation structure, the fins, and the dielectric fin; and one or more dielectric layers over sidewalls of the dummy gate stack. The method further includes removing the dummy gate stack to result in a gate trench within the one or more dielectric layers, wherein the dielectric fin is exposed in the gate trench; trimming the dielectric fin to reduce a width of the dielectric fin; and after the trimming, forming a high-k metal gate in the gate trench.