Dielectric Fin Gate Layout for GAA Poly Line Stability
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Solution Overview
Problem
In the semiconductor industry, the fabrication of gate-all-around (GAA) transistors faces challenges such as poly line collapse and defect issues due to high aspect ratios in the formation of gate structures, which affect device performance and reliability.
Innovation Solution
The integration of dielectric fin structures in the manufacturing process reduces the aspect ratio of gate structures, providing a strong base that prevents poly line collapse and supports the formation of high-k/metal gate structures without defects by ensuring the gate structures do not extend below the top of the semiconductor fins in cut oxide defined regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If gate structures are formed with high aspect ratios in GAA transistor fabrication, then device density and performance are improved, but poly line collapse and defect rates increase
Solution Approach 1:
The patent applies preliminary action by forming dielectric fins before gate structure formation. These dielectric fins are created in advance to provide mechanical support and reduce the aspect ratio of subsequent gate structures, preventing poly line collapse during the gate formation process while enabling higher device density
Solution Approach 2:
The dielectric fins act as an intermediary structure between the substrate and the gate electrodes. They provide a mechanical foundation that reduces the effective aspect ratio of the gate structures, allowing high-density GAA transistor fabrication without poly line collapse defects
2Reliability
If gate structures extend below the top of semiconductor fins in cut oxide defined regions, then device performance is improved, but defect issues increase
Solution Approach 1:
The dielectric fins are formed preliminarily to define the boundaries of where gate structures should extend. This preliminary structure prevents gate materials from extending below the semiconductor fin tops in cut oxide regions, eliminating defects while allowing performance-optimizing gate extensions in appropriate regions
Solution Approach 2:
The dielectric fins serve as an intermediary that controls gate structure geometry. They act as a physical barrier and guide for gate material deposition, ensuring gates extend to optimal lengths without protruding into defect-prone regions below the fin tops
Data Source
AI summary
A method of manufacturing an integrated circuit device is provided. The method includes forming a semiconductor fin over a semiconductor substrate; forming an isolation structure surrounding the semiconductor fin; etching a trench in the semiconductor fin; forming a dielectric fin in the trench; after forming the dielectric fin, recessing a top surface of the isolation structure, such that the dielectric fin and the semiconductor fin protrude from the recessed top surface of the isolation structure; and forming a first metal gate structure and a second metal gate structure over the dielectric fin and the semiconductor fin, respectively.