Dielectric Helmet BEOL Interconnects for Self-Aligned Via Scaling
Solution Overview
Problem
The scaling of features in integrated circuits poses challenges in controlling overlay tolerances and critical dimensions of vias, as lithographic equipment struggles to keep up with decreasing via pitches and critical dimensions, leading to issues with line width roughness and critical dimension uniformity, especially at nanometer scales, and requiring multiple masks which increases costs.
Innovation Solution
The implementation of a dielectric helmet-based approach for back end of line (BEOL) interconnect fabrication, using a non-conformal dielectric cap for selective growth or directed self-assembly, which eliminates the need for metal recess and allows for self-aligned interconnects at tight pitches, enabling improved via shorting margins and reduced process complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If lithographic processes are used to pattern vias, then via openings can be formed, but overlay tolerances and critical dimensions cannot be controlled sufficiently as via pitches and critical dimensions decrease to nanometer scales
Solution Approach 1:
The patent applies preliminary action by forming mandrels and spacers before the final via patterning step. The mandrels are deposited and patterned first, then spacers are formed around them, which serve as templates for the final via locations. This sequence allows precise control of via critical dimensions and pitch without relying solely on lithographic resolution at the final step, thereby resolving the contradiction between manufacturing precision and lithographic measurement difficulty.
2Quantity of substance
If via pitches are decreased to increase density, then more vias can be packed, but overlay tolerances become increasingly difficult to control
Solution Approach 1:
The patent employs self-service through self-aligned spacer formation. The spacers are deposited conformally on the mandrels and then anisotropically etched back, automatically positioning themselves with precise alignment to the mandrel features. This self-alignment mechanism eliminates the need for separate overlay alignment steps, enabling high via density while maintaining precise overlay tolerances even at reduced pitch dimensions.
3Manufacturing precision
If multiple lithographic masks are used to achieve small via pitches, then resolution can be improved, but process complexity and costs increase
Solution Approach 1:
The patent applies segmentation by dividing the via formation process into distinct stages: mandrel formation, spacer deposition, and via etching. The spacers act as segmented intermediate structures that define the final via pitch. This segmentation allows the final via pattern to be determined by the spacer dimensions rather than direct lithographic patterning, achieving high pitch resolution while using fewer lithographic masks and reducing overall process complexity.
Data Source
AI summary
Dielectric helmet-based approaches for back end of line (BEOL) interconnect fabrication, and the resulting structures, are described. In an example, a semiconductor structure includes a substrate. A plurality of alternating first and second conductive line types is disposed along a same direction of a back end of line (BEOL) metallization layer disposed in an inter-layer dielectric (ILD) layer disposed above the substrate. A dielectric layer is disposed on an uppermost surface of the first conductive line types but not along sidewalls of the first conductive line types, and is disposed along sidewalls of the second conductive line types but not on an uppermost surface of the second conductive line types.