Dielectric Interposer Layout for Multigate Source/Drain Leakage
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Solution Overview
Problem
Multigate devices, particularly gate-all-around transistors, face challenges with leakage current and stress loss in epitaxial source/drains due to scaling, which degrade performance and induce drain-induced-barrier-lowering effects.
Innovation Solution
Incorporation of sacrificial dielectric interposers, such as dummy oxide layers, between epitaxial source/drains to reduce leakage current and compensate for stress loss, using methods like selective etching and deposition processes to form bottom source/drain insulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If epitaxial source/drains are scaled down to improve device density, then device scaling is achieved, but leakage current increases and stress control deteriorates
Solution Approach 1:
A sacrificial dielectric interposer is introduced between the epitaxial source/drain and the substrate. This interposer acts as a mediator that provides bottom insulation to reduce leakage current while allowing the epitaxial source/drain to maintain its scaled dimensions for high device density. The dielectric material electrically isolates the source/drain from the substrate, preventing parasitic leakage paths.
Solution Approach 2:
The sacrificial dielectric interposer is formed before the final source/drain structure is completed. This preliminary action allows the interposer to be in place during subsequent processing steps, providing stress compensation and leakage prevention from the bottom up, before the source/drain is fully formed and scaled.
2Productivity
If epitaxial source/drains are scaled down to improve device density, then device scaling is achieved, but stress loss increases
Solution Approach 1:
The sacrificial dielectric interposer serves as a stress compensation layer between the scaled epitaxial source/drain and the substrate. It provides mechanical support and stress control from beneath, compensating for the stress loss that occurs when the source/drain dimensions are reduced for higher device density.
Solution Approach 2:
The dielectric constant and mechanical properties of the sacrificial interposer are carefully selected to match or compensate for the stress characteristics of the scaled epitaxial source/drain. By adjusting the interposer's material parameters, stress control is maintained even as the source/drain dimensions are reduced.
3Reliability
If sacrificial dielectric interposers are added to reduce leakage current, then leakage control improves, but device complexity increases
Solution Approach 1:
The sacrificial dielectric interposer is formed as a separate, distinct layer that can be selectively deposited and removed in specific regions. This extraction approach allows the interposer to be added only where needed for leakage control, rather than requiring a complete redesign of the entire device structure.
Solution Approach 2:
The sacrificial dielectric material is temporarily introduced during fabrication, performs its function of providing bottom insulation and stress control, and then is selectively removed or replaced in subsequent processing steps. This temporary presence allows complex functionality to be achieved without permanently increasing device structure complexity.
4Reliability
If bottom source/drain insulation is formed to reduce leakage current, then leakage control improves, but parasitic capacitance increases
Solution Approach 1:
The bottom source/drain insulation is applied locally only in regions where leakage control is needed, rather than as a universal blanket layer. By confining the dielectric material to specific areas beneath the source/drain, the insulation effect is maximized while the parasitic capacitance is minimized through reduced dielectric volume.
Solution Approach 2:
The thickness and dielectric constant of the bottom insulation layer are optimized to achieve the right balance between leakage reduction and capacitance control. By adjusting these parameters, sufficient electrical isolation is provided while keeping the parasitic capacitance contribution minimal.
Data Source
AI summary
Methods of fabricating multigate transistors using dummy oxide interposers are disclosed herein. An exemplary method includes forming a multilayer stack that includes first semiconductor layers, sacrificial semiconductor layers, and a substrate extension. A source/drain recess is formed by removing the first semiconductor layers, sacrificial semiconductor layers, and a portion of the substrate extension in a source/drain region, and a source/drain structure is formed in the source/drain recess. The source/drain structure includes a second semiconductor layer and an insulator layer, and the insulator layer is disposed between the second semiconductor layer and the substrate extension. Before forming the source/drain structure, the sacrificial semiconductor layers are replaced with sacrificial dielectric layers. After forming the source/drain structure, the sacrificial dielectric layers are removed from a channel region to form a portion of a gate opening. A gate stack is formed in the portion of the gate opening.