Dielectric Interposer Structure for Low-Leakage Semiconductor Packaging
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Solution Overview
Problem
Semiconductor devices face issues with current leakage and RC delay due to high dielectric constants in silicon interposers, limiting thickness reduction and overall device volume.
Innovation Solution
Employing a non-semiconductive dielectric interposer with a lower dielectric constant to interconnect electronic components, allowing for reduced thickness without interference, and using a multi-layered structure to compensate for structural mismatches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a silicon interposer is used to interconnect stacked electronic components, then interconnection between components is achieved, but current leakage and RC delay occur due to high dielectric constant
Solution Approach 1:
The patent changes the dielectric constant parameter by replacing silicon interposer with a low-k dielectric interposer having a dielectric constant of less than 3.5, thereby reducing current leakage and RC delay while maintaining interconnection functionality
Solution Approach 2:
The patent substitutes the expensive silicon interposer with a cheaper low-k dielectric material that achieves the same interconnection function with superior electrical performance, reducing both cost and harmful effects
2Volume of moving object
If thickness of silicon interposer is reduced, then device volume is minimized, but thickness reduction is restricted due to material property
Solution Approach 1:
The patent changes the material parameter from silicon to low-k dielectric material, enabling the interposer thickness to be reduced to 10 micrometers or less while maintaining structural integrity and preventing delamination
Solution Approach 2:
The patent employs a thin film low-k dielectric interposer with thickness of 10 micrometers or less, achieving minimal device volume while the flexible nature of the thin film structure allows for better stress distribution and reduced delamination risk
3Reliability
If non-semiconductive dielectric interposer with lower dielectric constant is used, then current leakage and RC delay are mitigated, but structural mismatch compensation is required
Solution Approach 1:
The patent uses a multi-layered composite structure combining low-k dielectric material with different k-values in each layer, where the first low-k dielectric layer has a dielectric constant of 2.5-3.0 and the second layer has a dielectric constant of 3.0-3.5, compensating for structural mismatches while maintaining low overall dielectric constant
Solution Approach 2:
The patent segments the dielectric interposer into multiple layers with different dielectric constants, allowing each layer to be optimized for specific functions: the first layer provides primary current leakage reduction, while the second layer compensates for structural mismatches and provides additional electrical performance optimization
Data Source
AI summary
A semiconductor device includes a dielectric interposer, a first RDL, a second RDL, and a plurality of conductive structures. The dielectric interposer has a first surface and a second surface opposite to the first surface. The first RDL is disposed over the first surface of the dielectric interposer. The second RDL is disposed over the second surface of the dielectric interposer. The conductive structures are disposed through the dielectric interposer and directly contact the dielectric interposer. The conductive structures are electrically connected to the first RDL and the second RDL. Each of the conductive structures has a tapered profile. A minimum width of each of the conductive structures is proximal to the first RDL, and a maximum width of each of the conductive structures is proximal to the second RDL.