Dielectric Isolation Structure for Monolithic Power MOSFET Integration

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Solution Overview

Problem

Current technologies face challenges in monolithically integrating different device types, such as vertical power MOSFETs and gate driver components, on the same semiconductor die, due to compatibility issues and electrical isolation requirements.

Innovation Solution

The implementation of a semiconductor device with a semiconductor substrate, an epitaxial layer or layer stack, and a combination of transistor cells of different types, where an isolation structure with dielectric material sidewalls and bottom electrically isolates these cells, allowing for their monolithic integration.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If different device types are monolithically integrated on the same semiconductor die, then efficiency and performance are improved, but electrical isolation and compatibility issues arise

Engineering Contradiction:
Improveintegration efficiencyVSAvoidelectrical interference
Core Design Contradiction:
ProductivityVSObject-affected harmful factors

Solution Approach 1:

The patent segments the semiconductor die into distinct regions separated by isolation structures. Different device types (vertical power MOSFETs and lateral transistors) are confined to specific segments, allowing monolithic integration while preventing electrical interference between them. The isolation structures create physical and electrical boundaries that maintain compatibility between different device types.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces isolation structures as intermediary elements between different device types. These isolation structures, comprising dielectric materials and doped semiconductor regions, act as mediators that enable coexistence of vertically conducting and laterally conducting devices on the same die while blocking harmful electrical interference between them.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Power

If vertical power MOSFETs and lateral transistors are integrated on the same die, then power handling capability is improved, but manufacturing complexity increases

Engineering Contradiction:
Improvecurrent handling capabilityVSAvoidstructural complexity
Core Design Contradiction:
PowerVSDevice complexity

Solution Approach 1:

The patent applies local quality by creating regions with different doping concentrations and types tailored to specific device requirements. High doping concentrations are localized in isolation structures and drift regions, while lower doping concentrations are used in active transistor regions. This localized variation in material properties enables integration of high-power vertical MOSFETs with lateral transistors without compromising either device type's performance or simplifying the manufacturing process.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS20250081621A1Semiconductor device having an isolation structure that delimits a region of an epitaxial layer or layer stack
Publication Date: 2025.03.06 INFINEON TECH AUSTRIA AG
  • US20250081621A1 patent drawing
  • US20250081621A1 patent drawing
  • US20250081621A1 patent drawing

AI summary

A semiconductor device includes: a semiconductor substrate; an epitaxial layer or layer stack on the semiconductor substrate; a plurality of transistor cells of a first type formed in a first region of the epitaxial layer or layer stack and electrically coupled in parallel to form a vertical power transistor; a plurality of transistor cells of a second type different than the first type and formed in a second region of the epitaxial layer or layer stack; and an isolation structure that laterally and vertically delimits the second region of the epitaxial layer or layer stack. Sidewalls and a bottom of the isolation structure include a dielectric material that electrically isolates the plurality of transistor cells of the second type from the plurality of transistor cells of the first type in the epitaxial layer or layer stack. Methods of producing the semiconductor device are also described.