Dielectric Isolation Structure for Merged Epitaxial Source/Drain Regions

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Solution Overview

Problem

As semiconductor devices are scaled down, the small spacing between adjacent transistors can cause epitaxial source/drain features to merge, leading to electrical shorting, which degrades device performance and reduces yield.

Innovation Solution

The formation of dielectric isolation structures between epitaxially grown source/drain components using a process that includes forming a thermally stable material layer, performing a gate replacement with high-k metal gate structures, etching openings to separate merged components, and filling these openings with a dielectric material to prevent electrical shorting.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If device geometry is scaled down to increase functional density, then production efficiency and cost are improved, but epitaxial source/drain features merge causing electrical shorting

Engineering Contradiction:
Improveproduction efficiencyVSAvoiddevice reliability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent applies segmentation by dividing the merged epitaxial source/drain region into separate components through etching openings and filling with dielectric material. This physically separates the source/drain features that would otherwise merge and cause electrical shorting, allowing continued device scaling while maintaining electrical isolation between adjacent transistors.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a dielectric material as an intermediary substance between the epitaxial source/drain regions. This dielectric fill material acts as a mediator that prevents direct electrical contact between merged source/drain features, enabling the device to maintain reliability even when geometric scaling causes physical merging of the epitaxial regions.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Area of stationary object

If spacing between adjacent transistors is reduced to increase functional density, then chip area utilization is improved, but electrical shorting between transistors occurs

Engineering Contradiction:
Improvechip area utilizationVSAvoidelectrical shorting
Core Design Contradiction:
Area of stationary objectVSObject-affected harmful factors

Solution Approach 1:

The patent segments the continuous merged epitaxial region by creating etching openings and filling them with dielectric material. This segmentation approach allows transistors to be placed closer together while maintaining electrical isolation, effectively enabling higher functional density without the harmful effect of electrical shorting.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent extracts the problematic conductive epitaxial material from the regions where it would cause shorting by etching openings through the merged source/drain regions. By removing the conductive material in strategic locations and replacing it with dielectric material, the harmful electrical connection is eliminated while preserving the close spacing needed for high density.

Inventive Principle:
Principle #2Taking out (Extraction)

3Ease of manufacture

If conventional fabrication methods are used for scaling, then manufacturing simplicity is maintained, but device performance degrades due to merging

Engineering Contradiction:
Improvemanufacturing simplicityVSAvoiddevice performance
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The patent applies preliminary action by performing etching of the merged epitaxial source/drain regions before final contact formation. This preliminary separation step ensures that the source/drain regions are divided into distinct components before subsequent processing steps, preventing electrical shorting from the outset and avoiding the need for complex remediation steps later in the fabrication process.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This solution effectively prevents electrical shorting between transistors, enhances device reliability and performance, and allows for simultaneous definition of source/drain contacts, reducing fabrication costs and processing time.

Implementation Method 1

gate replacement with high-k metal gate structures

Methodology Applied
Scientific EffectHigh-k dielectric: Dielectric Permittivity

Implementation Method 2

filling these openings with a dielectric material to prevent electrical shorting

Methodology Applied
Scientific EffectDielectric isolation: Dielectric Permittivity

Data Source

PatentUS11990525B2Isolation structure for isolating epitaxially grown source/drain regions and method of fabrication thereof
Publication Date: 2024.05.21 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11990525B2 patent drawing
  • US11990525B2 patent drawing
  • US11990525B2 patent drawing

AI summary

A first source/drain structure is disposed over a substrate. A second source/drain structure is disposed over the substrate. An isolation structure is disposed between the first source/drain structure and the second source/drain structure. The first source/drain structure and a first sidewall of the isolation structure form a first interface that is substantially linear. The second source/drain structure and a second sidewall of the isolation structure form a second interface that is substantially linear. A first source/drain contact surrounds the first source/drain structure in multiple directions. A second source/drain contact surrounds the second source/drain structure in multiple directions. The isolation structure is disposed between the first source/drain contact and the second source/drain contact.