Nanoinformatics TRIZ Cases

A SiOC liner on the isolation pattern shields exposed active regions in stacked-channel gate structures, reducing leakage current.

An added spacing layer and hard mask improve nanosheet gate height control during etch back while reducing cell capacitance.

A buried conductive pad inside shallow trench isolation gives GAA gate vias 2D routing paths, reducing layout area and central poly pitch.

A dopant diffusion barrier between stacked source/drain layers cuts resistance while mitigating short-channel effects in fin-type semiconductor devices.

Through-channel gates with negative capacitance enable multi-Vt nanosheet FETs on scaled GAA structures while cutting leakage and standby power.

An extended floating gate enlarges the sensing surface while shielding the nanostructure from liquid, improving biosensor sensitivity and reproducibility.

A high-Ge SiGe:B cap formed by melt-recrystallization boosts PMOS strain and lowers contact resistivity without dislocations.

Segmented LED wire growth with selective removal and transparent contacts reduces edge defects and parasitic growth for uniform wafer emission.

A laterally extended source/drain contact with two heights enables via access in tight transistor spacing while avoiding shorts.

A self-aligned grid layout forms quantum dot matrices with local chemical-potential control, uniform confinement, and simpler fabrication.

A self-aligned single-level grid layout controls quantum dot chemical potential and barriers while avoiding screening and tight alignment.

An annealed amorphous Ge-on-Si stack forms strain-relaxed single-crystal SiGe with controlled Ge concentration and fewer defects.

Work-function silicide on opposite source/drain surfaces lowers Schottky barriers and contact resistance in scaled semiconductor structures.

A conductive contact wraps epitaxial source/drain regions to use sidewall area and silicide conductivity for lower contact resistance.

Stacked colloidal quantum-dot photodiodes enable dual-band infrared detection with bias-controlled spectral selectivity and high optical fill factor.

A staggered stacked FET layout uses dielectric bonding and gate cuts to preserve gate control while shrinking semiconductor footprint.

Template-assisted selective epitaxy forms gate-aligned coupled quantum dots without extra confinement gates, supporting dense spin qubit scaling.

A capped low-k inner spacer protects against etching loss in replacement gate processing while cutting stray capacitance in multi-gate transistors.

Constrained oxygen or carbon monolayers create tensile strain in GAA nanostructures, boosting carrier mobility while limiting dopant diffusion.

A core-shell GaN nanofin switch uses a vertical superjunction structure to limit leakage and withstand high source-drain voltage.

An ONNO charge-trapping stack with oxygen-rich and oxygen-lean nitride layers cuts leakage, improves retention, and fits CMOS logic flows.

Internal hardmask stress can distort sub-micron patterns; this case uses heat treatment or a compensating layer to preserve fidelity.

An offset spacer enables deeper semiconductor contact trenches, expanding metal contact area to cut resistance and boost transistor performance.

Nitrogen-rich TiN wrapped around suspended nanosheets improves gate control, lowers threshold voltage, and suppresses short-channel effects.

A dielectric isolation pillar lets fork-sheet nanosheet CMOS shrink p/n spacing while improving electrostatics, mobility, and metal patterning.

H2-assisted lateral etching reshapes tapered vias with a wider bottom opening, lowering resistance in FinFET semiconductor structures.

Varying nanosheet counts across GAA transistor regions helps balance current while preserving precise self-aligned patterning at scaled nodes.

Selective molybdenum precursor deposition coats polysilicon uniformly while avoiding dielectric surfaces, improving semiconductor fabrication precision.

Self-aligned mandrels and spacers replace plasma etching to form uniform quantum dot gates with low-defect thermal oxide.

Three hardmasks and two spacers define uniform nanometre gate spacing, then transfer the pattern in one etch to avoid substrate damage.

Spacer-defined mandrels and thermal oxidation form uniform, low-defect quantum dot gates while reducing plasma etch damage to the substrate.

Stacked silicon and non-semiconductor monolayers boost carrier mobility, cut defects, and block dopant diffusion in enriched 28Si epitaxy.

Alternating oxygen and carbon monolayers in a silicon superlattice reshape band structure, boost carrier mobility, and limit dopant diffusion.

Dielectric-filled isolation cuts merged epitaxial source/drain regions to prevent transistor shorting while simplifying contact formation.

Extending the gate below the substrate adds sidewall control to curb standby leakage and threshold mismatch in nanostructure SRAM transistors.

A dual-step etch-back with dielectric plugs shapes uniform inner spacers and protects source/drain regions from void-causing etchant exposure.

A vertical BJT fin structure improves scaled-device electrical characteristics and reduces junction leakage while staying compatible with multi-bridge channel FETs.

Independent top and bottom fin control in stacked GAA structures helps tune n/p dimensions, limit threshold shifts, and cut parasitic RC.

Using SiAs or stacked SiP/SiAs epitaxy cuts phosphorus diffusion, boosts carrier mobility, and suppresses short-channel effects below 20 nm.

Selective channel doping in forksheet transistors balances SRAM read stability and write-ability without assist circuits, saving area and power.

Mechanical nanoindentation creates localized SiC junction defects for precise color center emission without complex ion implantation.