GAA Nanosheet Gate Stack With Nitrogen-Rich TiN Control
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Solution Overview
Problem
The challenge in fabricating horizontal gate-all-around (HGAA) transistors is the unsatisfactory nanosheet formation using current methods, particularly with a single epitaxial process, which leads to compromised gate control and increased short-channel effects due to scaling down of gate lengths.
Innovation Solution
A method for manufacturing gate-all-around FET devices involving the formation of fin structures with alternating semiconductor layers, use of sacrificial layers, and epitaxial growth of source/drain layers, followed by removal of sacrificial layers to create nanosheet channel regions, with a plasma-enhanced atomic layer deposition process for forming a nitrogen-rich titanium nitride work function layer to improve gate control and reduce threshold voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If gate lengths are scaled down to increase drive current, then transistor performance is improved, but gate control is compromised and short-channel effects increase
Solution Approach 1:
The patent transitions from planar gate structures to three-dimensional gate-all-around structures that wrap around the channel region. This dimensional change provides gate control from multiple directions (top, bottom, and sidewalls), significantly enhancing electrostatic control over the channel and mitigating short-channel effects while maintaining scaled dimensions.
Solution Approach 2:
The patent employs composite material structures including high-k dielectric materials combined with metal gate materials, and multi-layer channel structures with different semiconductor materials. These composite structures enable better electrostatic control and optimized carrier transport, allowing aggressive scaling while maintaining gate control and reducing short-channel effects.
2Ease of manufacture
If single epitaxial process is used for nanosheet formation, then process simplicity is maintained, but nanosheet formation quality is unsatisfactory
Solution Approach 1:
The patent divides the nanosheet formation process into multiple discrete epitaxial growth steps, each creating specific layers with controlled compositions and thicknesses. This segmentation allows precise control over nanosheet properties, interface quality, and layer stacking, achieving high manufacturing precision while maintaining a systematic fabrication approach.
Solution Approach 2:
The patent utilizes changes in epitaxial growth parameters including temperature, pressure, gas flow rates, and precursor ratios during different growth stages. By dynamically adjusting these parameters, the process achieves precise control over nanosheet formation, material composition, and crystal quality, transforming a simple single-step process into a sophisticated multi-parameter controlled fabrication sequence.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances gate control, reduces short-channel effects, and allows for aggressive scaling of transistors while maintaining performance by adjusting the atomic ratio of titanium to nitrogen in the work function layer, resulting in improved driving current and reduced threshold voltage.
Implementation Method 1
a plasma-enhanced atomic layer deposition process for forming a nitrogen-rich titanium nitride work function layer
Implementation Method 2
epitaxial growth of source/drain layers
Data Source
AI summary
A method of forming a semiconductor device includes forming a fin structure having a stack of alternating first semiconductor layers and second semiconductor layers over a substrate, the first semiconductor layers and the second semiconductor layers having different compositions, forming a dummy gate structure across the fin structure, forming gate spacers on opposite sidewalls of the dummy gate structure, respectively, removing the dummy gate structure to form a gate trench between the gate spacers, removing portions of the first semiconductor layers in the gate trench, such that the second semiconductor layers are suspended in the gate trench to serve as nanosheets, forming a first titanium nitride layer wrapping around the nanosheets, wherein an atomic ratio of titanium to nitrogen of the first titanium nitride layer is less than 1, and forming a metal fill layer over the first titanium nitride layer.