Multi-Layer Inner Spacers for Low-Capacitance Multi-Gate Transistors
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Solution Overview
Problem
As semiconductor technology advances to sub-10 nm technology nodes, existing low-k materials used as inner spacers in multi-gate transistors suffer from etching loss during the replacement gate process, leading to increased stray capacitance and reduced device performance.
Innovation Solution
The implementation of multi-layer inner spacers comprising a low-k dielectric layer and a capping layer that protects the low-k dielectric layer from etching loss, thereby reducing gate-to-drain and gate-to-source capacitance, and allowing for precise control of spacer thickness, shape, and location.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If low-k materials are used in inner spacers, then stray capacitance is reduced, but etching loss increases during replacement gate process
Solution Approach 1:
The patent applies composite materials by combining low-k dielectric material with a capping layer material to form a multi-layer inner spacer structure. The low-k layer reduces stray capacitance while the capping layer protects it from etching loss during the replacement gate process, resolving the contradiction between reducing capacitance and preventing material loss.
Solution Approach 2:
The capping layer acts as an intermediary protective layer that shields the low-k dielectric material from the etching process. This intermediary structure allows the low-k material to perform its capacitance-reducing function while being protected from direct exposure to etchants during gate replacement.
2Speed
If inner spacer thickness is reduced to control capacitance, then switching speed improves, but manufacturing precision becomes more difficult
Solution Approach 1:
The inner spacer is segmented into multiple layers with different functions: the low-k dielectric layer controls capacitance and switching speed, while the capping layer provides structural integrity and protects during processing. This segmentation allows independent optimization of each layer's thickness for its specific purpose, making manufacturing more controllable.
Solution Approach 2:
The patent changes the structural parameters of the inner spacer from a single-layer to a multi-layer configuration, allowing separate control of functional parameters (capacitance via low-k layer thickness) and structural parameters (overall stability via capping layer). This enables precise control of electrical characteristics without compromising manufacturing feasibility.
Data Source
AI summary
A semiconductor device includes semiconductor channel members disposed over a substrate, a gate dielectric layer disposed on and wrapping around the semiconductor channel members, a gate electrode layer disposed on the gate dielectric layer and wrapping around the semiconductor channel members, a source/drain (S/D) epitaxial layer in physical contact with the semiconductor channel members, and a dielectric spacer interposing the S/D epitaxial layer and the gate dielectric layer. The dielectric spacer includes a first dielectric layer in physical contact with the gate dielectric layer and a second dielectric layer in physical contact with the first dielectric layer. The first dielectric layer has a dielectric constant higher than that of the second dielectric layer. The second dielectric layer separates the first dielectric layer from physically contacting the S/D epitaxial layer.