Gate Recess Nanostructure Transistor for Threshold and Leakage Control
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Solution Overview
Problem
Nanostructure transistors face challenges such as standby leakage and threshold voltage mismatch issues due to inadequate gate control in bottom planar transistors, leading to performance degradation in SRAM devices.
Innovation Solution
The semiconductor device incorporates a gate structure that extends below the substrate surface for at least half of the channel width, providing extra sidewall gate control, and P-type epitaxial S/D features are deeper recessed than N-type, enhancing strain for improved on-current and reducing dopant out-diffusion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional gate structures are used in bottom planar transistors, then device fabrication is simpler, but gate control is inadequate leading to standby leakage and threshold voltage mismatch
Solution Approach 1:
The gate structure extends vertically into the substrate, transitioning from a planar surface-mounted configuration to a three-dimensional structure that wraps around the channel region. This vertical extension provides additional sidewall gate control surfaces, improving electrical control over the channel while maintaining compatibility with conventional fabrication processes.
2Reliability
If P-type and N-type epitaxial S/D features are at the same depth, then fabrication is simpler, but dopant out-diffusion and strain effects are not optimized
Solution Approach 1:
Different depths are provided for P-type and N-type epitaxial source/drain features based on their specific requirements. The P-type features extend deeper into the substrate to reduce dopant out-diffusion, while N-type features are positioned to optimize strain effects. This localized differentiation optimizes performance for each transistor type without requiring complete process redesign.
Data Source
AI summary
Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device includes a substrate including top portions isolated by an isolation structure, first semiconductor layers over a first top portion of the substrate in a first region, and a first gate structure wrapping each of the first semiconductor layers and covering a top surface and sidewalls of the first top portion of the substrate extending above the isolation structure. The first semiconductor layers are stacked up and separated from each other, and each first semiconductor layer has a first width. A bottom surface of the first gate structure is below the top surface of the substrate for a first depth which is at least half of the first width.