GAA Nanosheet Transistor Layout for Current-Balanced Scaling
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Solution Overview
Problem
The semiconductor industry faces challenges in scaling down transistor designs while maintaining performance and efficiency, particularly in achieving precise patterning of gate all-around (GAA) transistor structures for advanced semiconductor devices.
Innovation Solution
The manufacturing process involves forming semiconductor devices on substrates with alternating layers of sacrificial and channel materials, using photolithography and self-aligned processes to create patterned structures, and employing dummy gate structures and spacers to pattern semiconductor nanosheets, allowing for the formation of transistors with varying numbers of channel nanosheets to balance current and optimize performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If photolithography and self-aligned processes are used to pattern GAA transistor structures, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The patent divides the transistor structure into multiple discrete semiconductor nanosheets stacked vertically, with each nanosheet being a separate patternable layer. This segmentation allows independent patterning control of each nanosheet through photolithography, achieving high manufacturing precision while managing complexity through modular structure
Solution Approach 2:
The patent transitions from two-dimensional planar transistors to three-dimensional vertically-stacked nanosheet structures. By stacking multiple thin semiconductor layers in the vertical dimension, the design achieves higher effective channel width and improved patterning precision through self-aligned processes, while the vertical stacking manages the complexity by organizing multiple channels in the Z-direction rather than expanding laterally
2Reliability
If the number of channel nanosheets is varied to tune transistor performance, then electrical characteristics are improved, but manufacturing complexity increases
Solution Approach 1:
The patent applies local quality by allowing different device regions to have different numbers of semiconductor nanosheets (e.g., first device region with different count than second device region). This enables optimization of electrical characteristics for specific applications in specific regions while maintaining a standardized fabrication process, thus improving reliability without proportionally increasing overall manufacturing complexity
Solution Approach 2:
The patent changes the numerical parameter of nanosheet count to tune transistor performance characteristics such as drive current and threshold voltage. By varying this discrete parameter across different device regions or device types, the invention achieves customized electrical characteristics while using the same base fabrication process, managing complexity through parameter variation rather than process variation
3Productivity
If geometry size is scaled down to increase functional density, then productivity is improved, but manufacturing precision becomes more difficult to maintain
Solution Approach 1:
The patent moves critical dimensions from the lateral plane to the vertical stacking direction. By forming multiple nanosheets through vertical stacking of thin layers, the effective channel width is increased without requiring larger lateral footprint, thus maintaining high functional density and productivity while the vertical fabrication process maintains precision through controlled thin-film deposition and etching
Solution Approach 2:
The patent employs a nested structure where multiple semiconductor nanosheets are stacked one inside another in the vertical direction, similar to nested dolls. This nesting allows the transistor to achieve large effective channel width through vertical stacking rather than lateral expansion, maintaining small geometry size for high density while the nested structure enables precise patterning through self-aligned processes at each layer
Data Source
AI summary
A semiconductor device includes a semiconductor substrate, a first semiconductor stack, a second semiconductor stack, a first gate structure, and a second gate structure. The semiconductor substrate comprising a first device region and a second device region. The first semiconductor stack is located on the semiconductor substrate over the first device region, and has first channels. The second semiconductor stack is located on the semiconductor substrate over the second device region, and has second channels. A total number of the first channels is greater than a total number of the second channels. The first gate structure encloses the first semiconductor stack. The second gate structure encloses the second semiconductor stack.