Hardmask Spacer Patterning for Uniform Quantum Dot Gate Spacing
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Solution Overview
Problem
Current methods for manufacturing closely spaced gate structures in semiconductor quantum dot devices result in non-uniform dielectric spacing and gate heights, and expose the substrate to plasma etching, which damages the interface and degrades qubit performance.
Innovation Solution
A method using a combination of three hardmasks and two spacers to define nanometre-sized features without exposing the substrate to plasma etching, involving a series of masking material depositions and etching steps to create a final hardmask pattern that is transferred to the target layer in a single etching step, ensuring the substrate remains unaffected.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional multiple patterning methods are used to produce closely spaced gate structures, then the gate features can be formed, but the dielectric spacing between gates becomes non-uniform and gate heights become non-uniform
Solution Approach 1:
The patterning process is divided into multiple sequential steps using different mask types (first hardmask, second hardmask, third hardmask) and spacer formations. Each step creates a portion of the final pattern, with the first hardmask defining initial features, spacers providing precise spacing, and subsequent hardmasks adding additional features to achieve the complete closely-spaced gate structure with uniform dimensions
Solution Approach 2:
Spacers are introduced as intermediary structures between the hardmasks and the final gate features. These spacers serve as mediators that precisely define the dielectric spacing between gates through conformal deposition on the hardmask sidewalls, ensuring uniform spacing is transferred to the final gate structure without direct plasma etching of the underlying dielectric
2Ease of manufacture
If plasma etching is used during fabrication to pattern gates, then the gates can be formed, but the substrate interface is damaged and qubit performance deteriorates
Solution Approach 1:
The harmful plasma etching process is extracted and removed from the fabrication sequence that directly contacts the substrate interface. Instead, the patent uses a combination of hardmask depositions and spacer formations that pattern the gates through physical masking and conformal deposition, eliminating plasma exposure to the sensitive substrate-dielectric interface while still enabling precise gate patterning
Solution Approach 2:
Multiple disposable hardmask layers are used as sacrificial elements that are deposited, patterned, and removed in sequential steps. These temporary masks enable precise patterning without requiring plasma etching of the substrate, as they can be selectively removed after transferring their pattern to the final gate structure
3Quantity of substance
If consecutive gate patterning steps with overlapping gates are used, then gate features can be formed, but non-uniform dielectric spacing results
Solution Approach 1:
The first hardmask is deposited and patterned in advance to define the initial gate feature positions and dimensions. This preliminary patterning establishes a template that guides subsequent spacer formation, ensuring that the dielectric spacing is predetermined by the hardmask geometry before any overlapping gate features are created, thereby ensuring uniform spacing throughout the final structure
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables the production of closely spaced, uniform nanometre-sized features suitable for quantum dot devices without substrate damage, maintaining interface quality and improving qubit performance.
Implementation Method 1
producing a pair of first spacers respectively on the sidewalls of the blocks of the first hardmask... producing a second spacer on the exposed portions of the side surfaces of the blocks of the first hardmask and of the plurality of first blocks of masking material
Data Source
Figure 1~3
Figure 4~6
Figure 7~9
AI summary
The method applies a combination of three hardmasks (4,6,16) and depositions of masking material (5,15), together with the use of two spacers (8,18) for defining a distance between patterned features (3a-3g) down to a few nanometres. The steps of the method are configured to produce a final hardmask pattern on a target layer (3) wherein the final hardmask is subsequently transferred to the target layer in a single etching step, so that the surface onto which the target layer is formed is not affected by any process step prior to said final transfer. This ensures that the area underneath the pattern features remains unaffected by process steps such as plasma etching. The method is therefore very suitable for producing a pattern of closely spaced features which are suitable for use in a quantum dot device.