Nanosheet Multi-Channel Gate Stack for Height and Capacitance Control
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Solution Overview
Problem
The semiconductor industry faces challenges in controlling metal gate heights and reducing device capacitance as minimum feature size reduces, making it difficult to integrate more components in a given chip area while maintaining performance.
Innovation Solution
A method for manufacturing semiconductor devices involves forming nanosheet stacks with alternating semiconductor layers and a hard mask layer, followed by fin structure formation, isolation, and replacement gate processes to control gate height and reduce cell capacitance, using techniques like molecular beam epitaxy and chemical vapor deposition to achieve precise layer formation and etching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If minimum feature size is reduced to increase integration density, then more components can be integrated into a given chip area, but control of metal gate heights becomes challenging
Solution Approach 1:
The gate structure is segmented into multiple thin layers (first gate layer, second gate layer, third gate layer) rather than using a single thick gate layer. This segmentation allows each layer to be deposited and etched separately, providing better control over the overall gate height while maintaining high integration density through the multi-layer configuration.
Solution Approach 2:
The patent transitions from controlling gate height in a single dimension to controlling it through multiple stacked dimensions. By forming gate layers in vertical stacks with alternating orientations, the effective gate height control is achieved through the cumulative thickness of multiple thin layers rather than relying on precise control of a single thick layer.
2Productivity
If minimum feature size is reduced to increase integration density, then more components can be integrated into a given chip area, but device capacitance reduction becomes difficult
Solution Approach 1:
The gate structure is divided into multiple segmented layers with alternating orientations (first gate layer in first orientation, second gate layer in second orientation). This segmentation reduces the effective capacitance between adjacent gate structures by breaking up continuous conductive paths and reducing parasitic coupling, thereby addressing the capacitance issue while maintaining high integration density.
Solution Approach 2:
The patent employs asymmetric gate layer orientations where adjacent gate layers are positioned at different angles (first orientation versus second orientation). This asymmetric arrangement reduces capacitive coupling between neighboring gates by increasing effective spacing and reducing parallel plate capacitance effects, enabling better capacitance control at scaled dimensions.
3Manufacturing precision
If multi-layer gate structures are formed to control gate height, then manufacturing complexity increases, but gate height control improves
Solution Approach 1:
The patent forms alternating gate layers and isolation layers in a predetermined stacked sequence during the fabrication process. By establishing this alternating pattern early in the manufacturing process, subsequent etching and patterning steps can proceed more efficiently with better alignment control, reducing overall process complexity despite the multi-layer structure.
Solution Approach 2:
Isolation layers are introduced as intermediary elements between the conductive gate layers. These isolation layers serve as both structural spacers and etch stop layers, simplifying the manufacturing process by providing natural separation planes that facilitate precise thickness control of each gate layer without requiring complex independent deposition and etching sequences.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for improved control of gate height and reduced cell capacitance, enhancing device performance and integration density in semiconductor devices.
Implementation Method 1
forming fin structures including two or more channel layers and a hard mask layer over the two or more channel layers with spacing layers formed between adjacent channel layers and the hard mask layer
Implementation Method 2
followed by fin structure formation, isolation, and replacement gate processes to control gate height and reduce cell capacitance, using techniques like molecular beam epitaxy and chemical vapor deposition to achieve precise layer formation and etching
Data Source
AI summary
Embodiments of the present disclosure relate to forming a nanosheet multi-channel device with an additional spacing layer and a hard mask layer. The additional spacing layer provides a space for an inner spacer above the topmost channel. The hard mask layer functions as an etch stop during metal gate etch back, providing improve gate height control.