Single-Crystal SiGe Formation With Controlled Ge Diffusion
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing methods for forming silicon germanium (SiGe) hetero-structures using epitaxial growth or chemical vapor deposition often result in high germanium concentration leading to impurity defects and strain issues due to dislocation, which affect the performance of MOSFET devices.
Innovation Solution
A method involving the formation of an amorphous Ge layer on a Si layer, followed by an anneal process that allows germanium atoms to diffuse into the silicon layer, creating a crystal SiGe structure with reduced impurity defects and dislocations, and adjustable germanium concentration through thickness ratio control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If epitaxial growth or chemical vapor deposition is used to form SiGe hetero-structures, then germanium concentration can be increased to improve carrier mobility, but impurity defects and dislocation increase due to strain
Solution Approach 1:
The patent changes the formation parameters by using a two-step process: first forming an amorphous Ge layer, then annealing to create single crystalline SiGe. This parameter change allows achieving high Ge concentration (up to 100% in the channel) without the dislocation and impurity defects that plague conventional epitaxial growth methods.
Solution Approach 2:
The patent exploits phase transitions by forming an amorphous Ge layer that is subsequently transformed into single crystalline SiGe through annealing. This phase transition from amorphous to crystalline state enables the formation of high-quality SiGe structures without the defects associated with direct epitaxial growth, resolving the contradiction between high Ge concentration and defect formation.
2Reliability
If high germanium concentration is introduced into Si layer, then electron mobility in nMOS and hole mobility in pMOS are enhanced, but strain-induced dislocation occurs
Solution Approach 1:
The patent changes the structural parameters by introducing an intermediate amorphous Ge layer between the Si layer and the high-Ge-concentration channel. This parameter change allows the channel to achieve high Ge concentration for enhanced mobility while the intermediate layer absorbs strain, preventing dislocation.
Solution Approach 2:
The patent uses an intermediate amorphous Ge layer as a mediator between the Si layer and the high-Ge-concentration channel. This intermediate layer serves as a buffer that accommodates lattice mismatch and strain, enabling the channel to achieve high Ge concentration without dislocation, thus resolving the contradiction between mobility enhancement and strain-induced defects.
3Ease of manufacture
If conventional SiGe formation methods are used, then manufacturing process is established, but impurity defects reduce device performance
Solution Approach 1:
The patent changes the manufacturing parameters by replacing conventional single-step epitaxial growth with a two-step process involving amorphous Ge layer formation followed by annealing. This parameter change maintains manufacturability while dramatically improving device performance by eliminating impurity defects associated with conventional methods.
Solution Approach 2:
The patent utilizes phase transition from amorphous to crystalline state during annealing to transform the Ge layer into high-quality single crystalline SiGe. This approach maintains ease of manufacture through standard annealing processes while producing defect-free structures that significantly improve device performance, resolving the contradiction between manufacturability and performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method produces a strain-relaxed SiGe structure with improved mobility and reduced defects, suitable for integration in various transistor architectures, enhancing device performance by mitigating strain and impurity-related issues.
Implementation Method 1
anneal process that allows germanium atoms to diffuse into the silicon layer
Implementation Method 2
anneal process that allows germanium atoms to diffuse into the silicon layer, creating a crystal SiGe structure
Data Source
AI summary
A method of forming a semiconductor structure includes following operations. A substrate including a silicon (Si) layer is received. An amorphous germanium (Ge) layer is formed on the Si layer. A barrier layer is formed over the amorphous Ge layer. The substrate is annealed to transform the Si layer and the Ge layer to form a single crystalline SiGe layer. A Ge concentration is in a positive correlation with a ratio of a thickness of the Ge layer and a thickness of the Si layer.