Fork-Sheet Nanosheet CMOS Isolation Pillar for Electrostatic Scaling
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Solution Overview
Problem
Nanosheet device architectures face scaling limitations that result in electrostatic issues and mobility degradation, necessitating innovative solutions for improved performance and area scalability in semiconductor integrated circuits.
Innovation Solution
The implementation of a fork-sheet semiconductor structure with a dielectric isolation pillar separating p-type and n-type semiconductor regions, utilizing channel nanosheets of different materials to enhance operability and facilitate patterning challenges for work function metals, thereby addressing the limitations of traditional nanosheet FET devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional nanosheet FET device architecture is used, then device scaling is achieved, but electrostatic issues and mobility degradation occur
Solution Approach 1:
The device is segmented into multiple nanosheet channels (e.g., three channels) stacked vertically, allowing independent control and improved electrostatic characteristics for each channel while maintaining overall device scaling. This segmentation enables better gate control over each thin channel layer.
Solution Approach 2:
The invention transitions from planar 2D device architecture to vertical 3D stacking of multiple nanosheet channels. This dimensional change increases the effective channel width per footprint area while improving gate control and reducing electrostatic issues through the vertical configuration.
2Area of stationary object
If region separation between p-type and n-type devices is reduced, then area scalability is improved, but manufacturing complexity increases
Solution Approach 1:
The device structure is segmented with a central sacrificial layer that divides the device into symmetric p-type and n-type regions. This segmentation allows tighter spacing between regions while maintaining manufacturability through the use of a central reference structure for alignment.
Solution Approach 2:
While the overall structure appears symmetric, the invention uses asymmetric material selection (e.g., SiGe for p-type, Si for n-type) and asymmetric etching processes to create functionally distinct regions. This allows reduced spacing while maintaining device functionality through material-based differentiation rather than geometric asymmetry.
3Area of stationary object
If fork-sheet architecture is implemented, then p-type and n-type region separation is reduced, but patterning challenges for work function metals arise
Solution Approach 1:
The central sacrificial layer is formed preliminarily before the p-type and n-type nanosheet channels are created. This preliminary structure serves as a template and alignment reference that simplifies subsequent patterning of work function metals and other device components, making the overall manufacturing process easier despite the reduced region separation.
Solution Approach 2:
The central sacrificial layer acts as an intermediary structure that facilitates the patterning process. It provides a physical reference and spacing mechanism that enables precise placement of work function metals in the tightly-spaced fork-sheet architecture, solving the patterning challenge through this intermediate guiding structure.
Data Source
AI summary
A semiconductor structure includes a substrate, a first device disposed on the substrate and a second device disposed on the substrate. The first device includes a first plurality of nanosheets comprising a p-type material. The second device includes a second plurality of nanosheets comprising an n-type material. A dielectric isolation pillar is disposed between the first device and the second device.