FinFET Source/Drain Layering for Short-Channel and Resistance Control
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Solution Overview
Problem
The miniaturization of integrated circuit devices leads to a short channel effect, degrading their reliability, and it is challenging to mitigate this effect while reducing the resistance of the source/drain region effectively.
Innovation Solution
A semiconductor device is designed with a fin-type active region and a source/drain region that includes multiple material layers, with a dopant diffusion barrier layer between the layers to prevent dopant diffusion and reduce resistance, thereby mitigating the short channel effect.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the size of integrated circuit devices is reduced, then miniaturization is achieved, but short channel effect occurs degrading reliability
Solution Approach 1:
The source/drain region is divided into multiple material layers (first source/drain material layer, second source/drain material layer, etc.) with different properties. Each layer serves a specific function: lower layers provide stress control to mitigate short channel effect, while upper layers reduce resistance. This segmentation allows simultaneous optimization of multiple conflicting requirements in miniaturized devices.
Solution Approach 2:
The source/drain region employs composite material structure combining different semiconductor materials (e.g., SiGe, SiC, Si) with distinct electrical and mechanical properties. The composite structure enables stress engineering to control channel carrier mobility and mitigate short channel effect, while maintaining low resistance through appropriate material selection and doping strategies.
2Length of moving object
If the size of fin-type active region, gate line, and source/drain region is reduced, then miniaturization is achieved, but short channel effect degrades reliability
Solution Approach 1:
Different material layers are positioned at specific locations within the source/drain region to provide localized functions. For example, stress-inducing materials are placed adjacent to the channel region to locally modify stress conditions and mitigate short channel effect, while highly doped regions are positioned to reduce contact resistance without affecting channel characteristics.
Solution Approach 2:
The invention changes material composition parameters, doping concentrations, and layer thicknesses to optimize device performance. By adjusting Ge content in SiGe layers, doping levels in different regions, and relative thicknesses of source/drain layers, the device achieves both miniaturization and reliable operation despite reduced dimensions.
3Volume of moving object
If source/drain region size is reduced, then miniaturization is achieved, but resistance increases
Solution Approach 1:
The source/drain region uses composite material structure with multiple layers having different electrical properties. Upper layers are designed with high carrier concentration and low resistivity to reduce contact resistance, while lower layers provide stress control. This composite approach enables simultaneous achievement of miniaturization and low resistance through optimized material combination and layer configuration.
Solution Approach 2:
The multi-layer source/drain structure performs multiple functions simultaneously: stress engineering to control channel mobility, resistance reduction through high doping in contact regions, and short channel effect mitigation. Each layer contributes to one or more of these functions, making the structure universally beneficial for miniaturized devices.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces the resistance of the source/drain region and mitigates the short channel effect, enhancing the reliability of integrated circuit devices.
Implementation Method 1
a first dopant diffusion barrier layer on an interface between the first source/drain material layer and the second source/drain material layer
Data Source
AI summary
A semiconductor device includes: a fin-type active region extending on a substrate in a first direction that is parallel to an upper surface of the substrate; and a source/drain region in a recess region extending into the fin-type active region, wherein the source/drain region includes: a first source/drain material layer; a second source/drain material layer on the first source/drain material layer; and a first dopant diffusion barrier layer on an interface between the first source/drain material layer and the second source/drain material layer.